TPM-specific registers

Address

Name

Length

Description

Master access

0x34-0x37 Reserved

N/A

Read operations return 0xFF.

N/A

0x38-0x39

TPM_I2C_DEVICE_

ADDRESS

2

This register is used to change the I²C device

address.

Write-only

0x3A-0x3F Reserved

N/A

Read operations return 0xFF.

N/A

1. There are two ways to access TPM_HASH_START: the first is to write 0x04 to TPM_LOC_SEL followed by the write access

to TPM_HASH_START; the second is to write 0x04 to TPM_LOC_SEL, then to write the requestUse bit in TPM_ACCESS

followed by the write access to TPM_HASH_START.

3.3

Integration recommendations

3.3.1

I²C bus access load

The I²C host driver should take both the I²C bus load and the TPM load into account. This means that TPM

response availability checks have to be adapted to let enough time for the TPM to process the commands. ST

recommend using the interrupt mode on “response availability” events when possible as defined in the [PTP 2.0

r1.04] specification (§7.1.8). If the interrupt mode is not possible, a polling mechanism with an incremental delay

can also be used.

3.3.2

NACK on TPM I²C address

In §7.2.2.1.2 “Register write with address NACK”, the [PTP 2.0 r1.04] specification urges to repeat the current

cycle using the correct I²C device address and not to stop after the first NACK. ST recommend that the I²C host

driver repeats no less than eight times before considering the TPM I²C address NACK as true.

3.3.3

Hash locality 4 delay time to process command

After the HASH_DATA and HASH_END register commands, the TPM device makes specific cryptographic

calculations. During this time, I²C communication is not available and a NACK is sent. The unavailability duration

depends on the BYTE number and the HASH command type. The example below provides measurements for

an I²C frequency of 400 kHz with the default PCR configuration (SHA-256 and SHA-384 banks allocated). It is

possible to optimize the number of NACKs if only the SHA-256 bank is allocated with the TPM2_PCR_Allocate

command).

Example

32 bytes:

Hash data: < 10 µs → 0 Nack

Hash end: 3.77 ms → 85 Nack

64 bytes:

Hash data: 334 µs → 8 Nack

Hash end: 3.74 → 85 Nack

128 bytes:

Hash data: 1.08 ms → 24 Nack

Hash end: 3.77 ms → 85 Nack

1936 bytes:

Hash data: 13.7 ms → 311 Nack

Hash end: 3.84 ms → 87 Nack

3.3.4

I2C Linux driver

Refer to application note AN5714 Integrating the ST33TPHF2xSPI and ST33TPHF2xI2C trusted platform

modules with Linux® available at for information on how to integrate the TPM product over Linux.

ST33TPHF2XI2C

Integration recommendations

DS14167 - Rev 1

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