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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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80C554 датащи(PDF) 66 Page - NXP Semiconductors |
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80C554 датащи(HTML) 66 Page - NXP Semiconductors |
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66 / 76 page  Philips Semiconductors Preliminary specification 80C554/83C554/87C554 80C51 8-bit microcontroller – 6 clock operation 16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP 2000 Nov 10 66 AC ELECTRICAL CHARACTERISTICS VDD and Tamb minimum and maximum, per device specifications table; VSS = 0 V; CL = 100 pF for Port 0, ALE and PSEN; CL = 80 pF for all other outputs unless otherwise specified. 16 MHz CLOCK VARIABLE CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT External Program Memory 1/fCLK 49 System clock frequency, see Note 1 3.5 16 MHz tLHLL 49 ALE pulse width 37.5 – tCLK–25 – ns tAVLL 49 Address valid to ALE LOW 6.25 – 0.5 tCLK–25 – ns tLLAX 49 Address hold after ALE LOW 6.25 – 0.5 tCLK–25 – ns tLLIV 49 ALE LOW to valid instruction in – 60 – 2 tCLK–65 ns tLLPL 49 ALE LOW to PSEN LOW 6.25 – 0.5 tCLK–25 – ns tPLPH 49 PSEN pulse width 48.75 – 1.5 tCLK–45 – ns tPLIV 49 PSEN LOW to valid instruction in – 33.75 – 1.5 tCLK–60 ns tPXIX 49 Input instruction hold after PSEN 0 – 0 – ns tPXIZ 49 Input instruction float after PSEN – 6.25 – 0.5 tCLK–25 ns tAVIV 49 Address to valid instruction in – 76.25 – 2.5 tCLK–80 ns tPLAZ 49 PSEN LOW to address float – 10 – 10 ns External Data Memory tRLRH 50, 51 RD pulse width 87.5 – 3 tCLK–100 – ns tWLWH 50, 51 WR pulse width 87.5 – 3 tCLK–100 – ns tRLDV 50, 51 RD LOW to valid data in – 66.25 – 2.5 tCLK–90 ns tRHDX 50, 51 Data hold after RD 0 – 0 – ns tRHDZ 50, 51 Data float after RD – 42.5 – tCLK–20 ns tLLDV 50, 51 ALE LOW to valid data in – 100 – 4 tCLK–150 ns tAVDV 50, 51 Address to valid data in – 116.25 – 4.5 tCLK–165 ns tLLWL 50, 51 ALE LOW to RD or WR LOW 43.75 143.75 1.5 tCLK–50 1.5 tCLK+50 ns tAVWL 50, 51 Address valid to RD low or WR LOW 50 – 2 tCLK–75 – ns tQVWX 50, 51 Data valid to WR transition 1.25 – 0.5 tCLK–30 – ns tWHQX 51 Data hold after WR 6.25 – 0.5 tCLK–25 – ns tQVWH 50, 51 Data valid time WR HIGH 88.75 – 3.5 tCLK–130 – ns tRLAZ 50, 51 RD LOW to address float – 0 – 0 ns tWHLH 50, 51 RD or WR HIGH to ALE HIGH 6.25 56.25 0.5 tCLK–25 0.5 tCLK+25 ns External Clock tCHCX 52 High time 33.3 50 tCLK 0.4 tCLK 0.6 ns tCLCX 52 Low time 33.3 50 tCLK 0.4 tCLK 0.6 ns tCLCH 52 Rise time – 20 – 20 ns tCHCL 52 Fall time – 20 – 20 ns UART Timing – Shift Register Mode tXLXL 53 Serial port clock cycle time 500 – 6 tCLK – ns tQVXH 53 Output data setup to clock rising edge 179.5 – 5 tCLK –133 – ns tXHQX 53 Output data hold after clock rising edge 32.5 – tCLK–30 – ns tXHDX 53 Input data hold after clock rising edge 0 – 0 – ns tXHDV 53 Clock rising edge to input data valid – 179.5 – 5 tCLK–133 ns |
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