80C554 datasheet(64/76 Pages) PHILIPS

64 / 76 page

Philips Semiconductors

Preliminary specification

80C554/83C554/87C554

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM,

capture/compare, high I/O, 64L LQFP

2000 Nov 10

DC ELECTRICAL CHARACTERISTICS (Continued)

VDD and Tamb minimum and maximum, per device specifications table.

TEST

LIMITS

SYMBOL

PARAMETER

CONDITIONS

MIN

MAX

UNIT

Analog Inputs (Continued)

AVIN

Analog input voltage

AVSS–0.2

AVDD+0.2

AVREF

Reference voltage:

AVREF–

AVSS–0.2

AVREF+

AVDD+0.2

RREF

Resistance between AVREF+ and AVREF–

Ω

CIA

Analog input capacitance

tADS

Sampling time (10 bit mode)

8tCY

µs

tADS8

Sampling time (8 bit mode)

5tCY

µs

tADC

Conversion time (including sampling time, 10 bit mode)

50tCY

µs

tADC8

Conversion time (including sampling time, 8 bit mode)

24tCY

µs

DLe

Differential non-linearity10, 11, 12

±1

LSB

ILe

Integral non-linearity10, 13 (10 bit mode)

±2

LSB

ILe8

Integral non-linearity (8 bit mode)

±1

LSB

OSe

Offset error10, 14 (10 bit mode)

±2

LSB

OSe8

Offset error (8 bit mode)

±1

LSB

Gain error10, 15

±0.4

Absolute voltage error10, 16

±3

LSB

MCTC

Channel to channel matching

±1

LSB

Crosstalk between inputs of port 517, 18

0–100 kHz

–60

NOTES FOR DC ELECTRICAL CHARACTERISTICS:

1. See Figures 57 through 61 for IDD test conditions.

2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10 ns; VIL = VSS + 0.5 V;

VIH = VDD – 0.5 V; XTAL2 not connected; EA = RST = Port 0 = EW = VDD; STADC = VSS.

3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10 ns; VIL = VSS + 0.5 V;

VIH = VDD – 0.5 V; XTAL2 not connected; Port 0 = EW = VDD; EA = RST = STADC = VSS.

4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = EW = VDD;

EA = RST = STADC = XTAL1 = VSS.

5. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I2C specification, so an input voltage below 1.5 V will be recognized as a

logic 0 while an input voltage above 3.0 V will be recognized as a logic 1.

6. Pins of ports 1 (except P1.6, P1.7), 2, 3, and 4 source a transition current when they are being externally driven from 1 to 0. The transition

current reaches its maximum value when VIN is approximately 2 V.

7. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due

to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the

worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify

ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no

single output sinks more than 5 mA and no more than two outputs exceed the test conditions.

8. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 VDD specification when the

address bits are stabilizing.

9. The following condition must not be exceeded: VDD – 0.2 V < AVDD < VDD + 0.2 V.

10. Conditions: AVREF– = 0 V; AVDD = 5.0 V. Measurement by continuous conversion of AVIN = –20 mV to 5.12 V in steps of 0.5 mV, deriving

parameters from collected conversion results of ADC. AVREF+ (87C554) = 5.12 V. ADC is monotonic with no missing codes.

11. The differential non-linearity (DLe) is the difference between the actual step width and the ideal step width. (See Figure 48.)

12. The ADC is monotonic; there are no missing codes.

13. The integral non-linearity (ILe) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset error. (See Figure 48.)

14. The offset error (OSe) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and

a straight line which fits the ideal transfer curve. (See Figure 48.)

15. The gain error (Ge) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error),

and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. (See Figure 48.)

16. The absolute voltage error (Ae) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated

ADC and the ideal transfer curve.

17. This should be considered when both analog and digital signals are simultaneously input to port 5.

18. This parameter is guaranteed by design and characterized, but is not production tested.

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