AT25QL321 datasheet(9/82 Pages) RENESAS

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DS-AT25QL321-131 Rev. D

Page 9

Nov 1, 2022

AT25QL321 Datasheet

Table 1. Pin Descriptions

Symbol

Name and Function

Asserted

State

Type

CHIP SELECT

When this input signal is high, the device is deselected and serial data output pins are

at high impedance. Unless an internal program, erase or write status register cycle is

in progress, the device needs to be in the standby power mode (this is not the deep

power down mode). Driving Chip Select (CS) low enables the device, placing it in the

active power mode. After power-up, a falling edge on Chip Select (CS) is required prior

to the start of any command.

To ensure correct power-up sequencing, it is recommended to add a 10k Ohm pull-up

resistor from CS to VCC. This ensures CS ramps together with VCC during power-up.

Low

Input

SCK

SERIAL CLOCK

This input signal provides the timing for the serial interface. Commands, addresses, or

data present at serial data input are latched on the rising edge of Serial Clock (SCK).

Data are shifted out on the falling edge of the Serial Clock (SCK).

–

Input

SI (I/O0)

SERIAL INPUT

The SI pin is used to shift data into the device. The SI pin is used for all data input

including command and address sequences. Data on the SI pin is always latched in

on the rising edge of SCK.

With the Dual-Output and Quad-Output Read commands, the SI Pin becomes an

output pin (I/O0) in conjunction with other pins to allow two or four bits of data on (I/O3-

0) to be clocked in on every falling edge of SCK

To maintain consistency with the SPI nomenclature, the SI (I/O0) pin is referenced as

the SI pin unless specifically addressing the Dual-I/O and Quad-I/O modes in which

case it is referenced as I/O0.

Data present on the SI pin is ignored whenever the device is deselected (CS is

deasserted).

–

Input/Output

SO (I/O1)

SERIAL OUTPUT

The SO pin is used to shift data out from the device. Data on the SO pin is always

clocked out on the falling edge of SCK.

With the Dual-Output Read commands, the SO Pin remains an output pin (I/O0) in

conjunction with other pins to allow two bits of data on (I/O1-0) to be clocked in on

every falling edge of SCK

To maintain consistency with the SPI nomenclature, the SO (I/O1) pin is referenced as

the SO pin unless specifically addressing the Dual-I/O modes in which case it is

referenced as I/O1. The SO pin is in a high-impedance state whenever the device is

deselected (CS is deasserted).

–

Input/Output

WP (I/O2)

WRITE PROTECT / IO2

This pin is used either for write-protection, in which case it is referred to as WP, or as

one of the quad-SPI I/O pins, in which case it is referred to as IO2.

When the Quad Enable (QE) bit of Status Register 2 is 0, and the SRP1 and SRP0

bits are 0 and 1, respectively, the pin can be used for write-protection. It then can be

asserted (driven low) to protect the Status Registers from modification.

When the QE bit of Status Register 2 is 1, quad-SPI communication is enabled, and

the pin is used as I/O pin IO2 in any command that makes use of quad-SPI. In this

setting, do not use the pin for write-protection.

The WP pin does not have an internal pull-up; thus it must be either driven or, if not

used, pulled-up with an external resistor to Vcc.

–

Input/Output

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