23

3686I–DFLASH–02/2019

AT25DF321A

If the desire is to only change the SPRL bit without performing a Global Protect or Global Unprotect, then the system can

simply write a 0Fh to the first byte of the Status Register to change the SPRL bit from a logical “1” to a logical “0” provided

the WP pin is deasserted. Likewise, the system can write an F0h to change the SPRL bit from a logical “0” to a logical “1”

without affecting the current sector protection status (no changes will be made to the Sector Protection Registers).

When writing to the first byte of the Status Register, bits five, four, three and two will not actually be modified but will be

decoded by the device for the purposes of the Global Protect and Global Unprotect functions. Only bit seven, the SPRL bit,

will actually be modified. Therefore, when reading the first byte of the Status Register, bits five, four, three and two will not

reflect the values written to them but will instead indicate the status of the WP pin and the sector protection status. Please refer

to “Read Status Register” on page 30 and Table 11-1 on page 30 for details on the Status Register format and what values can be

read for bits five, four, three and two.

9.6

Read Sector Protection Registers

The Sector Protection Registers can be read to determine the current software protection status of each sector. Reading the

Sector Protection Registers, however, will not determine the status of the WP pin.

To read the Sector Protection Register for a particular sector, the CS pin must first be asserted and the opcode of 3Ch must be

clocked in. Once the opcode has been clocked in, three address bytes designating any address within the sector must be

clocked in. After the last address byte has been clocked in, the device will begin outputting data on the SO pin during every

subsequent clock cycle. The data being output will be a repeating byte of either FFh or 00h to denote the value of the

appropriate Sector Protection Register.

At clock frequencies above f

CLK, the first byte of data output will not be valid. Therefore, if operating at clock frequencies

above f

CLK, at least two bytes of data must be clocked out from the device in order to determine the correct status of the

appropriate Sector Protection Register.

Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS pin can be

deasserted at any time and does not require that a full byte of data be read.

In addition to reading the individual Sector Protection Registers, the Software Protection Status (SWP) bits in the Status

Register can be read to determine if all, some, or none of the sectors are software protected (refer to “Read Status Register” on

page 30

for more details).

Figure 9-5. Read Sector Protection Register

Table 9-3.

Read Sector Protection Register-Output Data

Output Data

Sector Protection Register Value

00h

Sector Protection Register value is 0 (sector is unprotected).

FFh

Sector Protection Register value is 1 (sector is protected).

SCK

CS

SI

SO

MSB

MSB

2

3

1

0

0

0

1

1

1

1

0

0

6

7

5

4

10 11

9

8

12

37 38

33

36

35

34

31 32

29 30

39 40

OPCODE

A

A

A

A

A

A

A

A

A

MSB

MSB

D

D

D

D

D

D

D

D

D

D

ADDRESS BITS A23-A0

DATA BYTE

HIGH-IMPEDANCE