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AT25DF321A датащи(PDF) 4 Page - Renesas Technology Corp

номер детали AT25DF321A
подробное описание детали  32-Mbit 2.7V Minimum Serial Peripheral Interface Serial Flash Memory
PDF  51 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

AT25DF321A датащи(HTML) 4 Page - Renesas Technology Corp

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3686I–DFLASH–02/2019
AT25DF321A
3.
Block Diagram
Figure 3-1. Block Diagram
4.
Memory Array
To provide the greatest flexibility, the memory array of the AT25DF321A can be erased in four levels of granularity including
a full chip erase. In addition, the array has been divided into physical sectors of uniform size, of which each sector can be
individually protected from program and erase operations. The size of the physical sectors is optimized for both code and data
storage applications, allowing both code and data segments to reside in their own isolated regions. The Memory Architecture
Diagram illustrates the breakdown of each erase level as well as the breakdown of each physical sector.
Figure 2-1.
8-SOIC (Top View)
Figure 2-2.
8-UDFN (Top View)
CS
SO (SOI)
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI (SIO)
FLASH
MEMORY
ARRAY
Y-GATING
CS
SCK
SO (SOI)
SI (SIO)
Y-DECODER
X-DECODER
I/O BUFFERS
AND LATCHES
CONTROL AND
PROTECTION LOGIC
SRAM
DATA BUFFER
WP
INTERFACE
CONTROL
AND
LOGIC
HOLD
CS
SO (SOI)
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI (SIO)



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