17

AT25DF011

DS-25DF011–032I–03/2022

of 77h must be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in

to specify the starting address location of the first byte to read within the OTP Security Register. Following the three

address bytes, two dummy bytes must be clocked into the device before data can be output.

After the three address bytes and the dummy bytes have been clocked in, additional clock cycles will result in OTP

Security Register data being output on the SO pin. When the last byte (00007Fh) of the OTP Security Register has been

read, the device will continue reading back at the beginning of the register (000000h). No delays will be incurred when

wrapping around from the end of the register to the beginning of the register.

Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS pin can

be deasserted at any time and does not require that a full byte of data be read.

Figure 10-2. Read OTP Security Register

11.

Status Register Commands

11.1 Read Status Register

The Status Register can be read to determine the device’s ready/busy status, as well as the status of many other

functions such as Hardware Locking and Block Protection. The Status Register can be read at any time, including during

an internally self-timed program or erase operation.The Status Register consists of two bytes.

To read the Status Register, the CS pin must first be asserted and the opcode of 05h must be clocked into the device.

After the opcode has been clocked in, the device will begin outputting Status Register data on the SO pin during every

subsequent clock cycle. After the last bit (bit 0) of Status Register Byte 1 has been clocked out, the first bit (bit 7) of

Status Register Byte 2 will be clocked out. After the last bit (bit 0) of Status Register Byte 2 has been clocked out, the

sequence will repeat itself, starting again with bit 7 of Status Register Byte 1, as long as the CS pin remains asserted and

the clock pin is being pulsed. The data in the Status Register is constantly being updated, so each repeating sequence

will output new data.

Deasserting the CS pin will terminate the Read Status Register operation and put the SO pin into a high-impedance

state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.

SCK

CS

SI

SO

MSB

MSB

23

1

0

01110111

67

5

410 11

9

812

33

36

35

34

31 32

29 30

OPCODE

AAAA

AAA

A

AX

X

X

MSB

MSB

DDDDDDD

D

D

D

ADDRESS BITS A23-A0

MSB

XXXXX

X

DON'T CARE

DATA BYTE 1

HIGH-IMPEDANCE

Table 11-1. Status Register Format

Bit(1)

Name

Type(2)

Description

7

BPL

Block Protection Locked

R/W

0

BP0 bit unlocked (default).

1

BP0 bit locked in current state when WP asserted.

6

RES

Reserved for future use

R

0

Reserved for future use.