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STM32U5A5QJ датащи(PDF) 41 Page - STMicroelectronics

номер детали STM32U5A5QJ
подробное описание детали  Ultra-low-power Arm® Cortex®-M33 32-bit MCUTrustZone®FPU,240 DMIPS, 4 MB Flash, 2.5 MB SRAM, LTDC, MIPI® DSI, crypto
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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STM32U5A5QJ датащи(HTML) 41 Page - STMicroelectronics

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DS13543 Rev 1
41/382
STM32U5Axxx
Functional overview
99
Stop 2
LPR
No
OFF
ON(5)
LSE
LSI
BOR, PVD, PVM,
RTC, TAMP, IWDG,
TEMP, VREFBUF,
ADC4,
DAC1 (2 channels),
COMPx (x = 1, 2) ,
OPAMPx (x = 1, 2),
LPUART1,
SPI3,
I2C3,
LPTIMx (x = 1,3,4),
ADF1,
LPGPIO,
LPDMA1
All other peripherals are frozen.
Reset pin, all I/Os
BOR, PVD, PVM,
RTC, TAMP, IWDG,
TEMP,
ADC4,
COMPx (x = 1, 2),
LPUART1,
SPI3,
I2C3,
LPTIMx (x = 1,3,4),
ADF1,
LPDMA1
Stop 3
LPR
No
OFF
ON(5)
LSE
LSI
BOR,
RTC, TAMP, IWDG,
DAC1 (2 static channels),
OPAMPx (x = 1, 2)
All other peripherals are frozen.
I/O configuration can be floating,
pull-up or pull-down.
Reset pin,
24 I/Os (WKUPx),
BOR, RTC, TAMP,
IWDG
Standby
LPR
OFF
LSE
LSI
BOR, RTC, TAMP, IWDG
All other peripherals are powered
off.
I/O configuration can be floating,
pull-up or pull-down.
Reset pin,
24 I/Os (WKUPx),
BOR, RTC, TAMP,
IWDG
OFF
Shutdown
OFF
OFF
LSE
RTC, TAMP
All other peripherals are powered
off.
I/O configuration can be floating,
pull-up or pull-down(15).
Reset pin
24 I/Os (WKUPx)
RTC, TAMP
Table 9. STM32U5Axxx modes overview (continued)
Mode
Regulator
(1)
CPU Flash SRAM Clocks
DMA and peripherals(2)
Wake-up source



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