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ADN2814XCPZ датащи(PDF) 3 Page - Analog Devices

номер детали ADN2814XCPZ
подробное описание детали  Continuous Rate 12.3 Mb/s to 675 Mb/s Clock and Data Recovery IC with Integrated Limiting Amp
PDF  28 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
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ADN2814XCPZ датащи(HTML) 3 Page - Analog Devices

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Preliminary Technical Data
ADN2814
Rev. PrA | Page 3 of 28
SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 µF, SLICEP = SLICEN = VEE, Input Data Pattern: PRBS 223 − 1,
unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
QUANTIZER—DC CHARACTERISTICS
Input Voltage Range
@ PIN or NIN, dc-coupled
1.8
2.8
V
Peak-to-Peak Differential Input
PIN – NIN
2.0
V
Input Common Mode Level
DC-coupled (see Figure 26, Figure 27,
and Figure 28)
2.3
2.5
2.8
V
Differential Input Sensitivity
223 − 1 PRBS, ac-coupled,1 BER = 1 x 10–10
10
6
mV p-p
Input Overdrive
(see Figure 11)
5
3
mV p-p
Input Offset
500
µV
Input RMS Noise
BER = 1 x 10–10
290
µV rms
QUANTIZER—AC CHARACTERISTICS
Data Rate
12.3
675
Mb/s
S11
@ 2.5 GHz
−15
dB
Input Resistance
Differential
100
Ω
Input Capacitance
0.65
pF
QUANTIZER—SLICE ADJUSTMENT
Gain
SLICEP – SLICEN = ±0.5 V
0.08
0.1
0.12
V/V
Differential Control Voltage Input
SLICEP – SLICEN
–0.95
+0.95
V
Control Voltage Range
DC level @ SLICEP or SLICEN
VEE
0.95
V
Slice Threshold Offset
1
mV
LOSS OF SIGNAL DETECT (LOS)
Loss of Signal Detect Range (see Figure 5)
RThresh = 0 Ω
12
15
17
mV
RThresh = 100 kΩ
2.0
3.0
4.0
mV
Hysteresis (Electrical)
GbE
RThresh = 0 Ω
5.0
6
7.0
dB
RThresh = 100 kΩ
3.0
6
8.0
dB
OC-1
RThresh = 0 Ω
5.6
6
7.2
dB
RThresh = 10 kΩ
2.0
4
6.7
dB
LOS Assert Time
DC-coupled2
500
ns
LOS De-Assert Time
DC-coupled2
400
ns
LOSS OF LOCK DETECT (LOL)
VCO Frequency Error for LOL Assert
With respect to nominal
1000
ppm
VCO Frequency Error for LOL De-Assert
With respect to nominal
250
ppm
LOL Response Time
12.3 Mb/s
4
ms
OC-12
1.0
µs
ACQUISITION TIME
Lock to Data Mode
OC-12
2.0
ms
OC-3
3.4
ms
OC-1
9.8
ms
12.3 Mb/s
40.0
ms
Optional Lock to REFCLK Mode
10.0
ms
DATA RATE READBACK ACCURACY
Coarse Readback
(See Table 13)
10
%
1 PIN and NIN should be differentially driven and ac-coupled for optimum sensitivity.
2 When ac-coupled, the LOS assert and de-assert time is dominated by the RC time constant of the ac coupling capacitor and the 50 Ω input termination of the
ADN2814 input stage.



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