ADN2814XCPZ datasheet(19/28 Pages) AD

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Preliminary Technical Data

ADN2814

Rev. PrA | Page 19 of 28

The two uses of the reference clock are mutually exclusive. The

reference clock can be used either as an acquisition aid for the

ADN2814 to lock onto data, or to measure the frequency of the

incoming data to within 0.01%. (There is the capability to

measure the data rate to approximately ±10% without the use of

a reference clock.) The modes are mutually exclusive, because,

in the first use, the user knows exactly what the data rate is and

wants to force the part to lock onto only that data rate; in the

second use, the user does not know what the data rate is and

wants to measure it.

Lock to reference mode is enabled by writing a 1 to I2C Register

Bit CTRLA[0]. Fine data rate readback mode is enabled by

writing a 1 to I2C Register Bit CTRLA[1]. Writing a 1 to both of

these bits at the same time causes an indeterminate state and is

not supported.

Using the Reference Clock to Lock onto Data

In this mode, the ADN2814 locks onto a frequency derived

from the reference clock according to the following equation:

Data Rate/2CTRLA[5:2] = REFCLK/2CTRLA[7:6]

The user must know exactly what the data rate is, and provide a

reference clock that is a function of this rate. The ADN2814 can

still be used as a continuous rate device in this configuration,

provided that the user has the ability to provide a reference

clock that has a variable frequency (see Application Note

AN-632).

The reference clock can be anywhere between 12.3 MHz and

200 MHz. By default, the ADN2814 expects a reference clock of

between 12.3 MHz and 25 MHz. If it is between 25 MHz and

50 MHz, 50 MHz and 100 MHz, or 100 MHz and 200 MHz, the

user needs to configure the ADN2814 to use the correct

reference frequency range by setting two bits of the CTRLA

Table 11. CTRLA Settings

CTRLA[7:6]

Range (MHz)

CTRLA[5:2]

Ratio

12.3 to 25

0000

25 to 50

0001

50 to 100

100 to 200

1000

256

The user can specify a fixed integer multiple of the reference

clock to lock onto using CTRLA[5:2], where CTRLA should be

set to the data rate/DIV_FREF, where DIV_FREF represents the

divided-down reference referred to the 12.3 MHz to 25 MHz

band. For example, if the reference clock frequency was

38.88 MHz and the input data rate was 622.08 Mb/s, then

CTRLA[7:6] would be set to [01] to give a divided-down

reference clock of 19.44 MHz. CTRLA[5:2] would be set to

[0101], that is, 5, because

622.08 Mb/s/19.44 MHz = 25

In this mode, if the ADN2814 loses lock for any reason, it

relocks onto the reference clock and continues to output a stable

clock.

While the ADN2814 is operating in lock to reference mode, if

the user ever changes the reference frequency, the FREF range

(CTRLA[7:6]), or the FREF ratio (CTRLA[5:2]), this must be

followed by writing a 0 to 1 transition into the CTRLA[0] bit to

initiate a new lock to reference command.

Using the Reference Clock to Measure Data Frequency

The user can also provide a reference clock to measure the

recovered data frequency. In this case, the user provides a

reference clock, and the ADN2814 compares the frequency of

the incoming data to the incoming reference clock and returns a

ratio of the two frequencies to 0.01% (100 ppm). The accuracy

error of the reference clock is added to the accuracy of the

ADN2814 data rate measurement. For example, if a 100-ppm

accuracy reference clock is used, the total accuracy of the

measurement is within 200 ppm.

The reference clock can range from 12.3 MHz and 200 MHz.

The ADN2814 expects a reference clock between 12.3 MHz and

25 MHz by default. If it is between 25 MHz and 50 MHz,

50 MHz and 100 MHz, or 100 MHz and 200 MHz, the user

needs to configure the ADN2814 to use the correct reference

frequency range by setting two bits of the CTRLA register,

CTRLA[7:6]. Using the reference clock to determine the

frequency of the incoming data does not affect the manner in

which the part locks onto data. In this mode, the reference clock

is used only to determine the frequency of the data. For this

reason, the user does not need to know the data rate to use the

reference clock in this manner.

Prior to reading back the data rate using the reference clock, the

CTRLA[7:6] bits must be set to the appropriate frequency range

with respect to the reference clock being used. A fine data rate

readback is then executed as follows:

Step 1: Write a 1 to CTRLA[1]. This enables the fine data rate

measurement capability of the ADN2814. This bit is level

sensitive and does not need to be reset to perform subsequent

frequency measurements.

Step 2: Reset MISC[2] by writing a 1 followed by a 0 to

CTRLB[3]. This initiates a new data rate measurement.

Step 3: Read back MISC[2]. If it is 0, then the measurement is

not complete. If it is 1, then the measurement is complete and

the data rate can be read back on FREQ[22:0]. The time for a

data rate measurement is typically 80 ms.

Step 4: Read back the data rate from registers FREQ2[6:0],

FREQ1[7:0], and FREQ0[7:0].

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