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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HC805K3GRS/D датащи(PDF) 29 Page - NXP Semiconductors |
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HC805K3GRS/D датащи(HTML) 29 Page - NXP Semiconductors |
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29 / 119 page  General Release Specification I/O and Control Registers MC68HC805K3 — Rev. 1.0 Memory Map 29 2.3 I/O and Control Registers The I/O and status/control registers reside in locations $0000–$001F. The overall organization of these registers is shown in Figure 2-2. The bit assignments for each register are shown in Figure 2-3 and Figure 2-4. Reading unimplemented bits returns unknown states, and writing to unimplemented bits has no effect. Figure 2-2. MC68HC805K3 I/O Registers Memory Map PORT A DATA REGISTER PORT B DATA REGISTER PORT A DATA DIRECTION REGISTER PORT B DATA DIRECTION REGISTER TIMER STATUS & CONTROL REGISTER TIMER COUNTER REGISTER PEEPROM STATUS & CONTROL REGISTER RESERVED UNIMPLEMENTED (2) UNIMPLEMENTED (2) UNIMPLEMENTED (3) UNIMPLEMENTED (10) IRQ STATUS & CONTROL REGISTER PORT A PULLDOWN REGISTER PORT B PULLDOWN REGISTER $0000 $0001 $0004 $0005 $0008 $0009 $001F $000A $0010 $0011 $000F $000F PEEPROM BIT SELECT REGISTER $000E MOR REGISTER 1 $0012 $0014 $0013 MOR REGISTER 2 RESERVED Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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