Data Sheet

LT3097

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 11 of 45

Table 3. Pin Function Descriptions (Continued)

Pin No.

Mnemonic

Description

6, 7

INN

Negative Input. The INN pins supply power to the negative regulator. The LT3097 requires a bypass capacitor at the INN pin. In general, the

output impedance of a battery rises with frequency; therefore, it is best practice to include a bypass capacitor in battery-powered applications.

While a 10 µF input bypass capacitor generally suffices, applications with large load transients can require higher input capacitance to prevent

input-supply droop. See the Stability and Input Capacitance and PSRR and Input Capacitance sections on the proper use of a negative input

capacitor and its effect on circuit performance, particularly negative regulator PSRR.

8

ENN/UVN

Negative Enable and UVLO. Pulling the ENN/UVN pin to GND moves the LT3097 negative regulator to shutdown mode. The negative quiescent

current in shutdown mode drops to 3 µA, and the negative output voltage turns off. Alternatively, the ENN/UVN pin can set a negative

input-supply UVLO threshold using a resistor-divider between INN, ENN/UVN, and GND. The ENN/UVN pin is bidirectional and can be switched

with either a positive or negative voltage. For positive voltages on the ENN/UVN pin, the LT3097 negative regulator typically turns on when the

ENN/UVN voltage exceeds 1.26 V above ground on its rising edge, with a 200 mV hysteresis on its falling edge. For negative voltages on the

ENN/UVN pin, the LT3097 negative regulator typically turns on when the ENN/UVN voltage exceeds 1.26 V below ground on its rising edge,

with a 215 mV hysteresis on its falling edge. If unused, connect ENN/UVN to INN. Do not float the ENN/UVN pin.

9

PGN

Negative Power Good. PGN is an open-collector flag that indicates negative output-voltage regulation. PGN pulls to GND if PGFBN is between

0 V and –300 mV. If the power-good functionality is not needed, float the PGN pin. The PGN flag status is valid even if the LT3097 negative

regulator is in shutdown, with the PGN pin being pulled to GND.

10

PGFBN

Negative Power-Good Feedback. The PGN pin pulls high if PGFBN is below –300 mV on its rising edge, with 7 mV hysteresis on its falling

edge. Connecting an external resistor-divider between OUTN, PGFBN, and GND sets the programmable power-good threshold with the

following transfer function: –0.3 V × (1 + RPGN2/RPGN1). In the Fast Startup section, PGFBN also activates the fast start-up circuitry. Connect

PGFBN to INN if the power-good and fast start-up functions are not needed.

11

ILIMN

Negative Regulator Current-Limit Programming Pin. Connecting a resistor between ILIMN and GND programs the current limit. For best

accuracy, Kelvin connects this resistor directly to the GND pin of the LT3097. The programming-scale factor is nominally 3.75 A × kΩ. If the

programmable current-limit functionality is not needed, connect ILIMN to GND. Do not float the ILIMN pin.

12

SETN

The Inverting Input of the Error Amplifier and the Regulation Set Point for the LT3097 Negative Regulator. SETN sinks precision 100 µA current

that flows through an external resistor connected between SETN and GND. The negative output voltage of the LT3097 is determined by VSETN

= ISETN × SETN resistance (RSETN). The negative output voltage range is from 0 V to –19.5 V. Adding a capacitor from SETN to GND improves

noise, PSRR, and transient response at the expense of an increased start-up time. Using the fast start-up capability through the PGFBN pin

mitigates this increase in start-up time. For optimum negative load regulation, Kelvin connects the ground side of the SETN pin resistor directly

to the negative load.

13

GND

Ground. Pin 13 is negative regulator ground.

14

OUTSN

Negative Output Sense. The OUTSN pin is the noninverting input to the error amplifier of the negative regulator. For optimal transient

performance and load regulation, Kelvin connects OUTSN directly to the negative output capacitor and the negative load. In addition, connect

the GND connections of the negative output capacitor and the SETN pin capacitor directly together. Exercise care regarding placement of

negative input capacitors relative to negative output capacitors due to potential PSRR degradation from magnetic coupling effects. See PSRR

and Input Capacitance for further information on capacitor placement and board layout. A parasitic-substrate diode exists between the OUTSN

and INN pins of the LT3097; therefore, do not drive OUTSN more than 0.3 V below INN during normal operation or during a fault condition.

15, 16

OUTN

Negative Output. The OUTN pins supply power to the negative load. For stability, use a minimum 10 µF output capacitor with an equivalent

series resistance (ESR) of less than 30 mΩ and an effective series inductance (ESL) of less than 1.5 nH. Large load transients require larger

output capacitance to limit peak-voltage transients. See the Stability and Output Capacitance section for more information on negative output

capacitance. A parasitic-substrate diode exists between the OUTN and INN pins of the LT3097; therefore, do not drive OUTN more than 0.3 V

below INN during normal operation or a fault condition.

17

PGFBP

Positive Power-Good Feedback. The PGP pin pulls high if PGFBP increases beyond 300 mV on its rising edge, with 7 mV hysteresis on its

falling edge. Connecting an external resistor-divider between OUTP, PGFBP, and GND sets the programmable power-good threshold with the

following transfer function: 0.3 V × (1 + RPGP2/RPGP1).In the Fast Startup section, PGFBP also activates the fast start-up circuitry. Connect

PGFBP to INP if the power-good and fast start-up functions are not needed. In addition, if reverse-input protection is additionally required,

connect the anode of a 1N4148 diode to INP and its cathode to PGFBP. A parasitic-substrate diode exists between the PGFBP and GND pin of

the LT3097; therefore, do not drive PGFBP more than 0.3 V below GND during normal operation or a fault condition.

18

SETP

The Inverting Input of the Error Amplifier and the Regulation Set Point for the LT3097 Positive Regulator. SETP sources precision 100 µA

current that flows through an external resistor connected between SETP and GND. The positive output voltage of the LT3097 is determined

by VSETP = ISETP × SETP resistance (RSETP). The positive output voltage range is from 0 V to 15 V. Adding a capacitor from SETP to GND

improves noise, PSRR, and transient response at the expense of an increased start-up time. Using the fast start-up capability through the

PGFBP pin mitigates this increase in start-up time. For optimum positive load regulation, Kelvin connects the ground side of the SETP pin

resistor directly to the positive load. A parasitic-substrate diode exists between the SETP and GND pins of the LT3097; therefore, do not drive

SETP more than 0.3 V below GND during normal operation or a fault condition.

19

GND

Ground. Pin 19 is positive regulator ground.