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DSP56307/D датащи(PDF) 13 Page - Motorola, Inc |
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DSP56307/D датащи(HTML) 13 Page - Motorola, Inc |
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13 / 156 page ![]() Signals/Connections External Memory Expansion Port (Port A) MOTOROLA DSP56307 Technical Data 1-7 External Data Bus External Bus Control Table 1-7 External Data Bus Signals Signal Name Type State During Reset Signal Description D0ÐD23 Input/ Output Tri-stated Data Bus ÑWhen the DSP is the bus master, D0ÐD23 are active-high, bidirectional input/outputs that provide the bidirectional data bus for external program and data memory accesses. Otherwise, D0ÐD23 are tri-stated. These lines have weak keepers to maintain the last state even if all drivers are tri-stated. Table 1-8 External Bus Control Signals Signal Name Type State During Reset Signal Description AA0ÐAA3 RAS0ÐRAS3 Output Output Tri-stated Address Attribute ÑWhen defined as AA, these signals can be used as chip selects or additional address lines. The default use defines a priority scheme under which only one AA signal can be asserted at a time. Setting the AA priority disable (APD) bit (Bit 14) of the OMR, the priority mechanism is disabled and the lines can be used together as four external lines that can be decoded externally into 16 chip select signals. Row Address Strobe ÑWhen defined as RAS, these signals can be used as RAS for DRAM interface. These signals are tri-statable outputs with programmable polarity. RD Output Tri-stated Read Enable ÑWhen the DSP is the bus master, RD is an active-low output that is asserted to read external memory on the data bus (D0ÐD23). Otherwise, RD is tri-stated. WR Output Tri-stated Write Enable ÑWhen the DSP is the bus master, WR is an active-low output that is asserted to write external memory on the data bus (D0ÐD23). Otherwise, the signals are tri-stated. Not Recommended for New Design |
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