DSP56307SLASHD datasheet(49/156 Pages) MOTOROLA

49 / 156 page

Specifications

Reset, Stop, Mode Select, and Interrupt Timing

MOTOROLA

DSP56307 Technical Data

2-13

Notes:

VCCQL = 2.5 V ± 0.25 V; TJ = Ð40ûC to +100ûC, CL = 50 pF

Periodically sampled and not 100% tested

For an external clock generator, RESET duration is measured during the time in which RESET is asserted,

VCC is valid, and the EXTAL input is active and valid.

For internal oscillator, RESET duration is measured during the time in which RESET is asserted and VCC

is valid. The specified timing reflects the crystal oscillator stabilization time after power-up. This number

is affected both by the specifications of the crystal and other components connected to the oscillator and

reflects worst case conditions.

When the VCC is valid, but the other Òrequired RESET durationÓ conditions (as specified above) have not

been yet met, the device circuitry will be in an uninitialized state that can result in significant power

consumption and heat-up. Designs should minimize this state to the shortest possible duration.

If PLL does not lose lock

When fast interrupts and IRQA are being used, then IRQB, IRQC, and IRQD are defined as

level-sensitive; timings 19 through 21 apply to prevent multiple interrupt service. To avoid these timing

restrictions, we recommend the deasserted edge-triggered mode when fast interrupts are being used.

Long interrupts are recommended when any level-sensitive mode is being used.

WS = number of wait states (measured in clock cycles, number of TC)

Use expression to compute maximum value.

This timing depends on several settings:

For PLL disable, if the internal oscillator (PLL Control Register (PCTL) Bit 16 = 0) is being used and the

oscillator is disabled during Stop (PCTL Bit 17 = 0), a stabilization delay is required to insure the oscillator

is stable before programs are executed. In that case, resetting the Stop delay (OMR Bit 6 = 0) will provide

the proper delay. While it is possible to set OMR Bit 6 = 1, it is not recommended and these specifications

do not guarantee timings for that case.

For PLL disable, if the internal oscillator (PCTL Bit 16 = 0) is being used and the oscillator is enabled

during Stop (PCTL Bit 17=1), then no stabilization delay is required, and recovery time will be minimal

(i.e., OMR Bit 6 setting is ignored).

For PLL disable, if the external clock (PCTL Bit 16 = 1) is being used, no stabilization delay is required,

and recovery time will be defined by the PCTL Bit 17 and OMR Bit 6 settings.

For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovery from Stop requires the

PLL to be locked. The duration of the PLL lock procedure (i.e., the PLL Lock Cycles (PLC)) may be in the

range of 0 to 1000 cycles. This procedure occurs in parallel with the stop delay counter, and stop recovery

will end when the last of these two events occurs. The stop delay counter completes count or PLL lock

procedure completion.

PLC value for PLL disable is 0.

The maximum value for ETC is 4096 (maximum MF) divided by the desired internal frequency. During

the stabilization period, TC, TH, and TL will not be constant, and their width may vary, so timing may

vary as well.

Table 2-7

Reset, Stop, Mode Select, and Interrupt Timing1 (Continued)

No.

Characteristics

Expression

100 MHz

Unit

Min

Max

Not Recommended for New Design

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