NSAM265SF datasheet(14/58 Pages) NSC

14 / 58 page

20 Functional Description (Continued)

TLEE12378 – 6

FIGURE 2-3 Codec Protocol - Short Frame

TLEE12378 – 7

FIGURE 2-4 Codec Protocol - Long Frame

25 DRAMARAM Access (NSAM265SR)

Reading from DRAM

A read bus cycle starts at T1 when the row address is driv-

en on the address bus and the data bus is in TRI-STATE

DWE is inactive (1) throughout the bus cycle One idle cycle

(TI) is guaranteed before a DRAM bus cycle

In the next clock cycle (T2W1) RAS is asserted (0) T2W2

and T2W3 follow the T2W1 bus cycle At T2W3 the column

address is driven onto the address bus A(010) (RA11 is in

TRI-STATE) Six T2W cycles and one T2 cycle follow At the

first T2W cycle the CAS signal is asserted (0) At the end of

T2 the NSAM265SR samples the data

The bus cycle is terminated with a T3 cycle when RAS and

CAS signals become inactive (1) To ensure enough DRAM

pre-charge time the DRAM read bus cycle is separated by

at least three clock cycles from any other DRAM bus cycle

(read write or refresh) Other bus cycles can start after at

least one TI (Idle) cycle

For more details refer to the timing diagram

Figure A-10

and ACDC specifications in ELECTRICAL CHARACTERIS-

TICS

Writing to DRAM

A write bus cycle starts at T1 when the row address is

driven on the address bus and the data bus is in TRI-

STATE One idle cycle (TI) is guaranteed before a DRAM

bus cycle

In the next clock cycle (T2W1) RAS is asserted (0) and the

data is available on the data bus (except for D2) T2W2 and

T2W3 follow the T2W1 cycle At T2W2 DWE is asserted (0)

to indicate the write operation

In the next cycle (T2W3) the column address is driven onto

the address bus A(010) and RA11 Then six T2W cycles

and one T2 cycle follow At the first T2W cycle CAS is

asserted (0)

The bus cycle is terminated by a T3 cycle when DWE RAS

and CAS signals become inactive (1) To provide enough

DRAM pre-charge time the DRAM write bus cycle is sepa-

rated by at least three clock cycles from any other DRAM

bus cycle (read write or refresh) Other bus cycles can start

after at least one TI cycle

For more details refer to the timing diagram

Figure A-11

and ACDC specifications in ELECTRICAL CHARACTERIS-

TICS

251 Refreshing a DRAMARAM

The NSAM265SR generates DRAM refresh bus cycles in

both normal operation and power-down modes In both cas-

es a clock generated by the clock generator sets the re-

fresh rate to

of the oscillator frequency

NSAM265SF датащи(PDF) 14 Page - National Semiconductor (TI)

NSAM265SF датащи(HTML) 14 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

датащи скачать

ссылки URL