M95128-DF datasheet(15/48 Pages) STMICROELECTRONICS

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6.3.4

SRWD bit

The Status register Write Disable (SRWD) bit is operated in conjunction with the Write protect (W) signal. The

Status register Write Disable (SRWD) bit and Write protect (W) signal enable the device to be put in the Hardware

Protected mode (when the Status register Write Disable (SRWD) bit is set to 1, and Write protect (W) is driven

low). In this mode, the non-volatile bits of the Status register (SRWD, BP1, BP0) become read-only bits and the

Write Status register (WRSR) instruction is no longer accepted for execution.

Table 6. Status register format

SRWD

BP1

BP0

WEL

WIP

Status register Write protect

Block protect bits

Write enable latch bit

Write in progress bit

6.4

Write Status register (WRSR)

The Write Status register (WRSR) instruction is used to write new values to the Status register. Before it can be

accepted, a Write enable (WREN) instruction must have been previously executed.

The Write Status register (WRSR) instruction is entered by driving Chip select (S) low, followed by the instruction

code, the data byte on Serial Data input (D) and Chip select (S) driven high. Chip select (S) must be driven high

after the rising edge of Serial clock (C) that latches in the eighth bit of the data byte, and before the next rising

edge of Serial clock (C). Otherwise, the Write Status register (WRSR) instruction is not executed.

The instruction sequence is shown in Figure 11 below.

Figure 11. Write Status register (WRSR) sequence

9 10

11 12 13 14 15

Instruction

MS47556V1

Status Register In

High impedance

MSB

Driving the Chip select (S) signal high at a byte boundary of the input data triggers the

self-timed Write cycle that takes tW to complete (as specified in AC tables in Section 9 DC and AC parameters).

While the Write Status register cycle is in progress, the Status register may still be read to check the value of the

Write in progress (WIP) bit: the WIP bit is 1 during the self-timed Write cycle tW, and 0 when the Write cycle is

complete. The WEL bit (Write enable latch) is also reset at the end of the Write cycle tW.

M95128-W M95128-R M95128-DF

Write Status register (WRSR)

DS1356 - Rev 20

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