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A31316 датащи(PDF) 57 Page - Allegro MicroSystems |
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A31316 датащи(HTML) 57 Page - Allegro MicroSystems |
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57 / 61 page ![]() 3D Magnetic Position Sensor IC A31316 57 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com DIG_OUT_PUSH_LIM (BITS 24:22) Selects the digital output push driver current limit. Approximate current limits are provided below: dig_out_push_lim Current Limit (mA) 0 10 1 8.75 2 7.5 3 6.25 4 5 5 3.75 6 2.5 7 1.25 DIG_OUT_PUSH_LIM_SEL (BIT 21) Disables the digital push driver current limit. • If dig_out_push_lim_dis = ‘0’ current limit is set by dig_out_ push_lim register. • If dig_out_push_lim_dis = ‘1’ current limit is ~20 mA SAT_COR_MASK (BIT 20) Disables the channel level saturation sub-flag when set. This mask only effects the error flag reporting ability and does not change the effects of saturation on the signal path data. SAT_FILT_MASK (BIT 19) Disables the filter level saturation sub-flag when set. This mask only effects the error flag reporting ability and does not change the effects of saturation on the signal path data. SAT_COR_MASK (BIT 18) Disables the saturation correction error flag when set. This mask only affects the error flag reporting ability. It does not change the effect of the saturation on the signal path data. SAT_LIN_MASK (BIT 17) Disables the saturation linearization error flag when set. This mask only affects the error flag reporting ability. It does not change the effect of the saturation on the signal path data. ACF_FAULT_FILT (BITS 16:15) Filters the ACF fault condition, the error condition must be present for the number of cycles shown below before a fault flag is tripped. acf_fault_filt Cycles 0 0 1 2 2 4 3 8 FAULT_FILT (BITS 14:12) Filters the SAT, AOC, and SRR flags; each error condition must be present for the number of cycles shown below before their respective flag is tripped. Additionally, also sets the number of temperature updates for which the temperature sensor must be in error before a TSE flag is set fault_filt SAT, AOC, SSR [Cycles] TSE [Temperature Updates] 0 0 1 1 2 2 2 4 4 3 8 8 4 16 16 5 32 2 6 64 4 7 128 8 OVD_MASK (BIT 11) Disables the overvoltage detection error flag when set. UVD_MASK (BIT 10) Disables the undervoltage detection error flag when set. SPE_MASK (BIT 9) Disables the signal path error flag when set. ESE_MASK (BIT 8) Disables the EEPROM single bit error flag when set. POR_MASK (BIT 7) Disables the power-on reset error flag when set. |
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