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A31316 датащи(PDF) 39 Page - Allegro MicroSystems

номер детали A31316
подробное описание детали  3D Magnetic Position Sensor IC
PDF  61 Pages
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производитель  ALLEGRO [Allegro MicroSystems]
домашняя страница  http://www.allegromicro.com
Logo ALLEGRO - Allegro MicroSystems

A31316 датащи(HTML) 39 Page - Allegro MicroSystems

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3D Magnetic Position Sensor IC
A31316
39
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
During a read command, the device determines the baud rate
from the sync bits and responds with a read response frame using
the same baud rate detected. The baud rate during a write com-
mand is also automatically detected, but is only used for decod-
ing, as the A31316 does not respond to write commands.
Table 26: Manchester Bit Definition (device response)
Quantity
of Bits
Name
Values
Description
2
Synchronization
00
Used to announce the
beginning of a Manchester
interface response
32
Data
Any
Read data
3
CRC
Any
Bits to check the validity of
frame.
The device memory contains non-volatile (EEPROM) and vola-
tile registers which are accessible via the serial interface through
Manchester communication modes. The memory address space is
divided into Factory and Customer areas.
MANCHESTER UNLOCKING – VIA OVD
1. At any time after POR, create an OVD condition. This sets
the OUT in HIGH-Z state since PWM/SENT Output is turned
off.
2. Send the correct access code.
3. Device is unlocked.
4. If manch_en bit was set LOW, the OVD condition can be
removed and the device returned to PWM/SENT Mode with
the device unlocked. OVD is needed for every Manchester
Read/Write command.
5. If manch_en bit was set HIGH, the OVD condition can be
removed, but the device will remain in communication mode.
OVD is not needed for Manchester transactions until manch_
en bit is set LOW through a Write Command. This action will
lock the device back.
MANCHESTER UNLOCKING – VIA TRIGGERING
PULSE
1. At any time after POR, create the trigger condition by driving
the output LOW for a specific amount of time depending
on the PWM (minimum of 2 full PWM messages) or SENT
Mode (minimum of 30 ttick). Then release the line or drive it
HIGH to create a 0→1 condition.
2. The device is in communication mode and a 300 µs timeout
starts.
3. Write the correct access code before the 300 µs expires. Tim-
ing requirements stop once the first sync bit is detected.
4. If the code is wrong, aborted, or it was an incorrect transac-
tion, the part goes back to PWM/SENT mode. Retrying by
starting at step 1 is possible.
5. If the code is correct, the device is unlocked and manch_en
bit is set to 1. The output is disabled, and the device remains
unlocked until manch_en is written to 0 through a Manches-
ter Write.
Table 27: Unlock Code and Customer Access Codes
Command
Write address
Write data
Customer access code
(Read access to factory)
manch_en = 1
0x86
0xC2D8E67B
Customer access code
(Read access to factory)
manch_en = 0
0x86
0xC2D8E67A
Manchester Communication CRC
The serial interface uses a cyclic redundancy check (CRC) for
data-bit error checking (synchronization bits are ignored during
the check). The CRC algorithm is based on the following polyno-
mial and the calculation is represented graphically in Figure 28.
The trailing 3 bits of a message frame comprise the CRC token.
The CRC is initialized at 111.
g(x) = x3 + x + 1
C0
C1
C2
Input Data
1x0
1x1
0x2
1x3
= x3 + x +1
Figure 28: Manchester CRC Implementation
EEPROM Lock
There are 3 different lock modes available in the A31316:
EELOCK, WRLOCK, and FLOCK. Each of these are separate
from access lock which requires a customer unlock code to con-
trol. EELOCK locks the EEPROM from external write access,
while still allowing writes to shadow and volatile registers.
The entirety of memory can still be read in this mode allowing
for a level of customer lock, while maintaining debug support.
WRLOCK prevents any write both EEPROM and volatile regis-
ters. Factory read support is maintained. This is not recommended
for any output mode. The FLOCK mode locks out both reads
and writes to EEPROM and all registers. This is will prevent any



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