LIS2DUX12 datasheet(33/102 Pages) STMICROELECTRONICS

33 / 102 page

Command

Command code

Default

Description

RSTGRPA

0x2C / 0x9C

Reset the group address

RSTACT

0x9A / 0x2A

Configure slave reset action

GETCAPS

0x95

0x00

0x11

0x18

0x00

Provide information about device capabilities and supported extended features

1. Direct RSTDAA can be disabled by writing bit DIS_DRSTDAA in I3C_IF_CTRL (33h) to 1.

6.3.3

Anti-spike filter management on mixed I²C/MIPI I3C® bus

In the LIS2DUX12, the SDA and SCL lines are common to both I²C and I3C. The I²C bus requires anti-spike filters

on the SDA and SCL pins that are not compatible with I3C timing.

The device acts as a standard I²C target as long as it is in deep power-down or in soft power-down with an I²C

static address.

When in deep power-down, the master must emit START, STATIC ADDRESS R/W (or dynamic address if

previously assigned) at open-drain speed using I²C fast mode plus reference timing to perform a power-up

command.

When the device is in soft power-down for the first time after a transition from the deep power-down state,

the device is capable of detecting and disabling the I²C anti-spike filter after detecting the broadcast address

(7'h7E/W). In order to guarantee proper behavior of the device, the I3C master must emit the first START,

7'h7E/W at open-drain speed using I²C fast mode plus reference timing.

After detecting the broadcast address, the device can receive the I3C dynamic address following the I3C push-

pull timing. If the device is not assigned a dynamic address, then it continues to operate as an I²C device with no

antispike filter. For the case in which the host decides to keep the device as I²C with an anti-spike filter, there is a

configuration required to keep the anti-spike filter active. This configuration is done by writing the ASF_ON bit to 1

in the I3C_IF_CTRL (33h) register. This configuration forces the anti-spike filter to always be turned on instead of

being managed by the communication on the bus.

LIS2DUX12

MIPI I3C® interface

DS14071 - Rev 2

page 33/102

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