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MCP6S93 датащи(PDF) 8 Page - Microchip Technology

номер детали MCP6S93
подробное описание детали  Single-Ended, Rail-to-Rail I/O, Low-Gain PGA
PDF  40 Pages
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производитель  MICROCHIP [Microchip Technology]
домашняя страница  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP6S93 датащи(HTML) 8 Page - Microchip Technology

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 2004 Microchip Technology Inc.
DS21908A-page 8
MCP6S91/2/3
FIGURE 1-5:
Detailed SPI™ Serial Interface Timing; SPI 1,1 Mode.
1.1
DC Output Voltage Specs / Model
1.1.1
IDEAL MODEL
The ideal PGA output voltage (VOUT) is:
EQUATION 1-1:
(see Figure 1-6). This equation holds when there are
no gain or offset errors and when the VREF pin is tied to
a low-impedance source (<< 0.1
Ω) at ground potential
(VSS = 0V).
1.1.2
LINEAR MODEL
The PGA’s linear region of operation, including offset
and gain errors, is modeled by the line VO_LIN shown in
Figure 1-6.
EQUATION 1-2:
The end points of this line are at VO_ID = 0.3V and
VDD – 0.3V. Figure 1-6 shows the relationship between
the gain and offset specifications referred to in the
electrical specifications as follows:
EQUATION 1-3:
The DC Gain Drift (
∆G/∆T
A) can be calculated from the
change in gE across temperature. This is shown in the
following equation:
EQUATION 1-4:
CS
SCK
SI
tSU tHD
tCSSC
tSCCS
SO
(first 16 bits out are always zeros)
tDO
tSOZ
tHI
tLO
1/fSCK
tCS1
tCSH
tCS0
Where:
G is the nominal gain
V
O_ID
G
VIN
=
V
REF
V
SS
0V
==
V
O_LIN
G1
g
E
+
() V
IN
0.3V
G
-----------
V
OS
+
–


0.3V
+
=
V
REF
V
SS
0V
==
g
E
100%
V
2
V
1
–
GV
DD
0.6V
–
()
--------------------------------------
=
V
OS
V
1
G1
g
E
+
()
-------------------------
=
G+1
=
G
∆
T
A
∆
⁄
g
E
∆
T
A
∆
----------
=



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