Philips Semiconductors

Product specification

74F573/74F574

Latch/flip-flop

1989 Oct 16

4

LOGIC DIAGRAM – 74F573

D0

D1

D2

D3

D4

D5

D6

D7

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

E

OE

23

4

5

6

789

12

13

14

15

16

17

18

19

1

11

E

D

Q

E

D

Q

EQ

D

E

D

Q

E

D

Q

E

D

Q

E

D

Q

E

D

Q

GND=Pin 10

SF01079

FUNCTION TABLE – 74F573

INPUTS

INTERNAL

OUTPUTS

OPERATING MODES

OE

E

Dn

REGISTER

Q0 – Q7

OPERATING MODES

L

L

H

H

L

H

L

H

L

H

Load and read register

L

L

↓

↓

l

h

L

H

L

H

Latch and read register

L

L

X

NC

NC

Hold

H

H

L

H

X

Dn

NC

Dn

Z

Z

Disable outputs

H = High voltage level

h = High voltage level one setup time prior to the High-to-Low E transition

L = Low voltage level

l

= Low voltage level one setup time prior to the High-to-Low E transition

NC= No change

X = Don’t care

Z = High impedance “off” state

↓ = High-to-Low E transition

LOGIC DIAGRAM – 74F574

D0

D1

D2

D3

D4

D5

D6

D7

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

CP

OE

23

4

5

6

789

12

13

14

15

16

17

18

19

1

11

CP

D

Q

CP

D

Q

CP

Q

D

CP

D

Q

CP

D

Q

CP

D

Q

CP

D

Q

CP

D

Q

GND=Pin 10

SF01080