Philips Semiconductors

Product specification

74F573/74F574

Latch/flip-flop

74F573 Octal Transparent Latch (3-State)

74F574 Octal D Flip-Flop (3-State)

2

1989 Oct 16

853-0083 97897

FEATURES

interface to Microprocessors

respectively

DESCRIPTION

The 74F573 is an octal transparent latch coupled to eight 3-State

output buffers. The two sections of the device are controlled

independently by Enable (E) and Output Enable (OE) control gates.

The 74F573 is functionally identical to the 74F373 but has a

broadside pinout configuration to facilitate PC board layout and

allow easy interface with microprocessors.

The data on the D inputs is transferred to the latch outputs when the

Enable (E) input is High. The latch remains transparent to the data

input while E is High and stores the data that is present one setup

time before the High-to-Low enable transition.

The 3-State output buffers are designed to drive heavily loaded

3-State buses, MOS memories, or MOS microprocessors. The

active Low Output Enable (OE) controls all eight 3-State buffers

independent to the latch operation. When OE is Low, the latched or

transparent data appears at the outputs. When OE is High, the

outputs are in high impedance “off” state, which means they will

neither drive nor load the bus.

The 74F574 is functionally identical to the 74F374 but has a

broadside pinout configuration to facilitate PC board layout and

allow easy interface with microprocesors.

It is an 8-bit, edge triggered register coupled to eight 3-State output

buffers. The two sections of the device are controlled independently

by the clock (CP) and Output Enable (OE) control gates.

The register is fully edge-triggered. The state of each D input, one

setup time before the Low-to-High clock transition is transferred to

the corresponding flip-flop’s Q output.

The 3-State output buffers are designed to drive heavily loaded

3-State buses, MOS memories, or MOS microprocessors. The

active Low Output Enable (OE) controls all eight 3-State buffers

independently of the latch operation. When OE is Low, the latched

or transparent data appears at the outputs. When OE is High, the

outputs are in high impedance “off” state, which means they will

neither drive nor load the bus.

TYPE

TYPICAL

PROPAGATION DELAY

TYPICAL SUPPLY

CURRENT

(TOTAL)

74F573

5.0ns

35mA

TYPE

TYPICAL SUPPLY

CURRENT

(TOTAL)

74F574

180MHz

50mA

ORDERING INFORMATION

DESCRIPTION

COMMERCIAL RANGE

PKG DWG #

20-Pin Plastic DIP

N74F573N, N74F574N

SOT146-1

20-Pin Plastic SOL

N74F573D, N74F574D

SOT163-1

20-Pin Plastic SSOP

N74F573DB

SOT339-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

DESCRIPTION

74F (U.L.)

HIGH/LOW

LOAD VALUE

HIGH/LOW

D0 - D7

Data inputs

1.0/1.0

20

µA/0.6mA

E (74F573)

Latch Enable input (active falling edge)

1.0/1.0

20

µA/0.6mA

OE

Output Enable input (active Low)

1.0/1.0

20

µA/0.6mA

CP (74F574)

Clock Pulse input (active rising edge)

1.0/1.0

20

µA/0.6mA

Q0 - Q7

3-State outputs

150/40

3.0mA/24mA

NOTE: One (1.0) FAST Unit Load is defined as: 20

µA in the High state and 0.6mA in the Low state.