Philips Semiconductors

Product specification

74F273A

Octal D flip–flop

1996 Mar 12

3

LOGIC SYMBOL (IEEE/IEC)

SF00348

1

32

4

5

7

6

8

9

R

11

C1

13

12

14

15

17

16

18

19

1D

LOGIC DIAGRAM

CP

Q

RD

D

3

D0

Q0

CP

Q

RD

D

4

D1

CP

Q

RD

D

7

D2

CP

Q

RD

D

8

D3

CP

Q

RD

D

13

D4

CP

Q

RD

D

14

D5

CP

Q

RD

D

17

D6

CP

Q

RD

D

18

D7

2

Q1

5

Q2

6

Q3

9

Q4

12

Q5

15

Q6

16

Q7

19

11

1

CP

MR

VCC = Pin 20

GND = Pin 10

SF00349

FUNCTION TABLE

INPUTS

OUTPUTS

OPERATING

MR

CP

Dn

Q0 – Q7

MODE

L

X

X

L

Reset (clear)

H

↑

h

H

Load ”1”

H

↑

l

L

Load ”0”

H = High voltage level

h

= High voltage level one set–up time prior to the Low–to–High clock transition

L

= Low voltage level

l

= Low voltage level one set–up time prior to the Low–to–High clock transition

X = Don’t care

↑ = Low–to–High clock transition