74F273AD datasheet(2/10 Pages) PHILIPS

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Philips Semiconductors

Product specification

74F273A

Octal D flip–flop

1996 Mar 12

853–0066 16555

FEATURES

• High impedance inputs for reduced loading

(20

µA in Low and High states)

• Ideal buffer for MOS microprocessor or memory

• Eight edge–triggered D–type flip–flops

• Buffered common clock

• Buffered asynchronous Master Reset

• See 74F377A for clock enable version

• See 74F373 for transparent latch version

• See 74F374 for 3–State version

DESCRIPTION

The 74F273 has eight edge–triggered D–type flip–flops with

individual D inputs and Q outputs. The common buffered Clock (CP)

and Master Reset (MR) inputs load and reset (clear) all flip–flops

simultaneously.

The register is fully edge–triggered. The state of each D input, one

setup time before the Low–to–High clock transition, is transferred to

the corresponding flip–flop’s Q output.

All outputs will be forced Low independently of Clock or Data inputs

by a Low voltage level on the MR input. The device is useful for

applications where the true output only is required and the CP and

MR are common to all elements.

TYPE

TYPICAL

fMAX

TYPICAL SUPPLY CURRENT

(TOTAL)

74F273A

170MHz

25mA

ORDERING INFORMATION

PACKAGES

COMMERCIAL RANGE

VCC = 5V±10%;

Tamb = 0°C to +70°C

PKG. DWG. #

20–pin plastic DIP

74F273AN

SOT146-1

20–pin plastic SOL

74F273AD

SOT163-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

DESCRIPTION

74F(U.L.)

HIGH/LOW

LOAD VALUE

HIGH/LOW

D0 – D7

Data inputs

1.0/0.033

µA/20µA

Master Reset input (active–Low)

1.0/0.033

µA/20µA

Clock pulse input (active rising edge)

1.0/0.033

µA/20µA

Q0 – Q7

Data outputs

50/33

1.0mA/20mA

PIN CONFIGURATION

GND

VCC

SF00346

LOGIC SYMBOL

VCC = Pin 20

GND = Pin 10

SF00347

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