ADP3192

Rev. 0 | Page 27 of 32

The limit of the peak per-phase current described earlier during

the secondary current limit is determined by

()

()

MAX

DS

D

BIAS

CLAMPED

COMP

PHLIM

R

A

V

V

I

×

−

≅

(34)

2.8 mΩ (low-side on resistance at 150°C) results in a per-phase

peak current limit of 64 A. This current level can be reached only

with an absolute short at the output, and the current-limit latch-off

function shuts down the regulator before overheating can occur.

FEEDBACK LOOP COMPENSATION DESIGN

Optimized compensation of the ADP3192 allows the best

possible response of the regulator output to a load change. The

basis for determining the optimum compensation is to make the

regulator and output decoupling appear as an output impedance

that is entirely resistive over the widest possible frequency

With the resistive output impedance, the output voltage droops

in proportion to the load current at any load current slew rate.

This ensures optimal positioning and minimizes the output

decoupling.

Because of the multimode feedback structure of the ADP3192,

the feedback compensation must be set to make the converter

output impedance work in parallel with the output decoupling

to make the load look entirely resistive. Compensation is

needed for several poles and zeros created by the output

inductor and the decoupling capacitors (output filter).

A type-three compensator on the voltage feedback is adequate

for proper compensation of the output filter. Equation 35 to

Equation 39 are intended to yield an optimal starting point for

the design; some adjustments may be necessary to account for

PCB and component parasitic effects (see the Tuning the

ADP3192 section).

First, compute the time constants for all the poles and zeros in the system using Equation 35 to Equation 39.

(

)

VID

O

X

RT

VID

RT

L

DS

D

O

E

V

R

C

n

V

D

n

L

V

V

R

R

A

R

n

R

×

×

×

×

×

−

×

×

+

×

+

×

+

×

=

1

2

(

)

Ω

m

9

.

2

2

V

1.3

Ω

m

1

mF

6

.

5

4

V

51

0.

0.432

1

nH

320

2

V

1.3

V

51

0.

Ω

m

1.4

Ω

m

2.4

5

Ω

m

1

4

=

×

×

×

×

−

×

×

+

×

+

×

+

×

=

E

R

(35)

()

()

μs

0

0

.

3

Ω

m

0.6

Ω

m

0.5

Ω

m

1

Ω

m

1

pH

0

24

Ω

m

0.5

Ω

m

1

mF

6

.

5

'

'

=

−

×

+

−

×

=

−

×

+

−

×

=

X

O

O

X

O

X

A

R

R

R

R

L

R

R

C

T

(36)

(

)

(

)

ns

0

6

5

mF

6

.

5

Ω

m

1

Ω

m

0.5

Ω

m

0.6

'

=

×

−

+

=

×

−

+

=

X

O

X

B

C

R

R

R

T

(37)

μs

17

.

5

Ω

m

9

.

2

2

V

1.3

kHz

330

2

Ω

m

2.4

5

nH

320

V

51

0.

2

=

×

⎟

⎟

⎠

⎞

⎜

⎜

⎝

⎛

×

×

−

×

=

×

⎟

⎟

⎠

⎞

⎜

⎜

⎝

⎛

×

×

−

×

=

E

VID

SW

DS

D

RT

C

R

V

f

R

A

L

V

T

(38)

()

(

)

()

ns

8

33

Ω

m

1

μF

180

Ω

m

0.5

Ω

m

1

mF

6

.

5

Ω

m

1

μF

180

mF

6

.

5

'

2

2

=

×

+

−

×

×

×

=

×

+

−

×

×

×

=

O

Z

O

X

O

Z

X

D

R

C

R

R

C

R

C

C

T

(39)

where:

R' is the PCB resistance from the bulk capacitors to the ceramics.

In this example,

the 10 Al-Poly capacitors.