LTC3113 datasheet(21/32 Pages) AD

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LT3154

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

PCB LAYOUT CONSIDERATIONS

The LT3154 switches large currents at high frequencies.

Special attention should be paid to the PCB layout to en‑

sure a stable, noise‑free and efficient application circuit.

Figure 4 presents a representative PCB layout for the

LT3154 to outline some of the primary considerations. A

few key guidelines are outlined below:

1. All circulating high current paths should be kept as

short as possible. This can be accomplished by keeping

the routes to all bold boxed components in Figure 4 as

short and as wide as possible. Capacitor ground con‑

nections should via down to the ground plane in the

shortest route possible. The bypass capacitors on PVIN

and PVOUT to PGND should be placed as close to the

IC as possible and should have the shortest possible

paths to ground. These connections should be made

as wide as possible to reduce the series resistance.

This will improve efficiency and maximize the output

current capability of the buck‑boost converter.

2. The exposed pad is the power ground connection for

the LT3154. Multiple vias should connect the back‑

pad directly to the ground plane. In addition maximi‑

zation of the metallization connected to the back‑pad

will improve the thermal environment and improve the

power handling capabilities of the IC.

3. The components shown in bold boxes and their con‑

nections should all be placed over a complete ground

plane to minimize loop cross‑sectional areas. This

minimizes EMI and reduces inductive drops.

4. Keep the connection from the resistor dividers (R3,

R4) to the FB pin as short as possible and away from

the switch pin connections, return to the ground plane

close to the IC.

Compensation of the Buck-Boost Converter

The LT3154 utilizes an average current architecture to

regulate the output voltage. Average current mode control

has two loops that require frequency compensation, the

inner average current loop and the outer voltage loop. The

compensation for the inner average current loop is fixed to

simplify the loop design and provide the highest possible

bandwidth over a wide operating range.

Figure 4. Example PCB Layout, Top Layer is Shown, Bottom Layer is Mostly PGND Plane

CIN

PVIN

PGND

CIN

PGND

SW1

SW2

COUT

PVOUT

COUT

PGND

3154 F05

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