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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC855T датащи(PDF) 50 Page - NXP Semiconductors |
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MPC855T датащи(HTML) 50 Page - NXP Semiconductors |
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50 / 77 page  MPC860 PowerQUICC Family Hardware Specifications, Rev. 10 50 Freescale Semiconductor CPM Electrical Characteristics Figure 51. SI Receive Timing Diagram with Normal Clocking (DSC = 0) 84 L1CLK edge to L1CLKO valid (DSC = 1) — 30.00 ns 85 L1RQ valid before falling edge of L1TSYNC4 1.00 — L1TCL K 86 L1GR setup time2 42.00 — ns 87 L1GR hold time 42.00 — ns 88 L1CLK edge to L1SYNC valid (FSD = 00) CNT = 0000, BYT = 0, DSC = 0) — 0.00 ns 1 The ratio SYNCCLK/L1RCLK must be greater than 2.5/1. 2 These specs are valid for IDL mode only. 3 Where P = 1/CLKOUT. Thus, for a 25-MHz CLKO1 rate, P = 40 ns. 4 These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC, whichever comes later. Table 19. SI Timing (continued) Num Characteristic All Frequencies Unit Min Max L1RXD (Input) L1RCLK (FE = 0, CE = 0) (Input) L1RCLK (FE = 1, CE = 1) (Input) L1RSYNC (Input) L1ST(4–1) (Output) 71 72 70 71a RFSD=1 75 73 74 77 78 76 79 BIT0 |
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