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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC855T датащи(PDF) 33 Page - NXP Semiconductors |
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MPC855T датащи(HTML) 33 Page - NXP Semiconductors |
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33 / 77 page  MPC860 PowerQUICC Family Hardware Specifications, Rev. 10 Freescale Semiconductor 33 Bus Signal Timing Table 8 provides interrupt timing for the MPC860. Figure 23 provides the interrupt detection timing for the external level-sensitive lines. Figure 23. Interrupt Detection Timing for External Level Sensitive Lines Figure 24 provides the interrupt detection timing for the external edge-sensitive lines. Figure 24. Interrupt Detection Timing for External Edge Sensitive Lines Table 8. Interrupt Timing Num Characteristic1 1 The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as level-sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference to the CLKOUT. The timings I41, I42, and I43 are specified to allow the correct function of the IRQ lines detection circuitry and have no direct relation with the total system interrupt latency that the MPC860 is able to support. All Frequencies Unit Min Max I39 IRQx valid to CLKOUT rising edge (setup time) 6.00 — ns I40 IRQx hold time after CLKOUT 2.00 — ns I41 IRQx pulse width low 3.00 — ns I42 IRQx pulse width high 3.00 — ns I43 IRQx edge-to-edge time 4 × T CLOCKOUT —— CLKOUT IRQx I39 I40 CLKOUT IRQx I41 I42 I43 I43 |
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