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RT9204CS датащи(PDF) 10 Page - Richtek Technology Corporation |
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RT9204CS датащи(HTML) 10 Page - Richtek Technology Corporation |
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10 / 14 page ![]() RT9204 Preliminary www.richtek-ic.com.tw DS9204-00 February 2002 10 Input / Output Capacitor High frequency/long life decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance to the PCB trace, as it could eliminate the performance from utilizing these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. The output capacitors are necessary for filtering output and stabilizing the close loop (see the PWM loop stability). For powering advanced, high-speed processors, it is required to meet with the requirement of fast load transient, high frequency capacitors with low ESR/ESL capacitors are recommended. Another concern is high ESR induced ripple may trigger UV or OV protections. Linear Regulator Driver The linear regulator of RT9204 was designed to drive bipolar NPN or MOSFET pass transistor. For MOSFET pass transistor, normally DRV need to provide minimum VOUT2+VT+gate-drive voltage to keep VOUT2 as setting voltage. When driving MOSFET operating at 5V power supply system, the gate-drive will be limited at 5V. In this situation shown in Fig. 5, low VT threshold MOSFET (VT = 1V) and Vout2 setting below 2.5V were suggested. In VBOOT = 12V operation condition as Fig. 6, VCC is regulated as higher to 6V providing more gate-drive for pass MOSFET transistor, VOUT2 can be set as ≤ 3.3V. Fig. 5 Fig. 6 PWM Loop Stability The RT9204 is a voltage mode buck controller designed for 5V step-down applications. The gain of error amplifier is fixed at 35dB for simplified design. The output amplitude of ramp oscillator is 1.6V, the loop gain and loop pole/zero are calculated as follows: DC loop gain GA = 35dB × × LC filter pole PO = × π × Error Amp pole PA = 300kHz ESR zero ZO = × π × ESR × C The RT9204 Bode plot as shown Fig.7 is stable in most of application conditions. + FBL VCC RT9204 VOUT2 ≤ 2.5V R3 BOOT DRV VCC = 5V R4 R4 < 1K + FBL VCC RT9204 VOUT2 ≤ 3.3V R3 BOOT DRV VBOOT = 12V R4 R4 < 1K 6V Loop Gain VOUT = 1.5V VOUT = 2.5V VOUT = 3.3V ZO = 3.2kHz PO = 2.9kHz L=2µH COUT = 1500µF(33mΩ) VOUT = 3.3V 40 30 20 10 1M 100k 10k 1k 100 Fig. 7 LC 2 1 2 1 6 . 1 5 VOUT 8 . 0 |
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