AS1500 datasheet(4/8 Pages) AMSCO

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Data Sheet AS1500/1/2/3

Revision 1.0, Oct 2004

Page 4 of 8

AS1502 / AS1503 – SPECIFICATIONS

VDD = 3V±10% or 5V±10%, VA = VDD, VB = 0V, –40°C

≤ TA ≤ +125°C unless otherwise noted.

ELECTRICAL CHARACTERISTICS – 50k and 100k VERSIONS

Parameter

Symbol

Conditions

Min

Typ12

Max

Unit

DC CHARACTERISTICS RHEOSTAT MODE

TA = 25°C, VDD = 5V, AS1502, Version: 50k

Ω

Nominal Resistance13

RAB

TA = 25°C, VDD = 5V, AS1503, Version: 100k

Ω

100

120

Ω

Resistance Tempco14

∆RAB/∆T VAB = VDD, Wiper = No Connect

500

ppm/°C

Wiper Resistance

VDD = 5V

100

200

Ω

Resistor Differential NL15

R-DNL

RWB, VDD = 5V, VA = No Connect

–1

±1/4

LSB

Resistor Integral NL

R-INL

RWB, VDD = 5V, VA = No Connect

–2

±1/2

LSB

DC CHARACTERISTICS POTENTIOMETER DIVIDER

Resolution

Bits

VDD = 5.5V TA = 25°C

–4±1+4

LSB

Integral Nonlinearity

INL

VDD = 2.7V TA = 25°C

–4±1+4

LSB

VDD = 5.5V TA = 25°C

–1

±1/4

LSB

Differential Nonlinearity

DNL

VDD = 2.7V TA = 25°C

–1

±1/4

LSB

Voltage Divider Tempco

∆VW /∆T Code = 80H

ppm/°C

Full-Scale Error

VWFSE

Code = FFH, VDD = 5.5V

–1

–0.25

LSB

Zero-Scale Error

VWZSE

Code = 00H, VDD = 5.5V

0.1

LSB

RESISTOR TERMINALS

Voltage Range16

VA, B, W

0VDD

Capacitance17 Ax, Bx

CA, B

f = 1MHz, Measured to GND, Code = 80H

Capacitance Wx

f = 1MHz, Measured to GND, Code = 80H

DIGITAL INPUTS AND OUTPUTS

Input Logic High

VIH

VDD = 5V

2.4

Input Logic Low

VIL

VDD = 5V

0.8

Input Logic High

VIH

VDD = 3V

2.1

Input Logic Low

VIL

VDD = 3V

0.6

Input Current

IIH, IIL

VIN = 5V or 0V, VDD = 5V

±1

µA

Input Capacitance

CIL

5pF

POWER SUPPLIES

Power Supply Range

VDD

2.7

5.5

Supply Current (CMOS)

IDD

VIH = VDD or VIL = 0V, VDD = 5.5V

0.1

µA

Supply Current (TTL)18

IDD

VIH = 2.4V or 0.8V, VDD = 5.5V

0.9

Power Dissipation

(CMOS)19

PDISS

VIH = VDD or VIL = 0V, VDD = 5.5V

27.5

µW

AS1502, Version: 50k

Ω

-43

tbd.

Power Supply Suppression

Ratio

PSSR

VDD = 5V + 0.5VP

sine wave @ 1kHz

AS1503, Version:

100k

Ω

-48

tbd.

DYNAMIC CHARACTERISTICS20

BW_50k RWB = 50kΩ, VDD = 5V

220

kHz

Bandwidth –3dB

BW_100k RWB = 100kΩ, VDD = 5V

110

kHz

Total Harmonic Distortion

THDW

VA = 1VRMS + 2VDC, VB = 2VDC, f = 1kHz

0.003

tS_50k

RWB = 50k

Ω, VA = VDD, VB = 0V, ±1% Error

Band

9µs

VW Settling Time

tS_100k RWB = 100kΩ, VA = VDD, VB = 0V, ±1% Error

Band

µs

eNWB_50k RWB = 50kΩ, f = 1kHz

nV/

√ Hz

Resistor Noise Voltage

eNWB_100

RWB = 100k

Ω, f = 1kHz

nV/

√ Hz

Table 4: Electrical Characteristics – 50k and 100k Versions

Typicals represent average readings at 25°C and VDD = 5V.

Wiper is not connected. IAB = 70µA for the 50k

Ω version and 35µA for the 100kΩ version.

All Tempcos are guaranteed by design and not subject to production test.

Terminal A is not connected. IW = 70µA for the 50k

Ω version and 35µA for the 100kΩ version.

Resistor terminals A, B, W have no limitations on polarity with respect to each other.

All capacitances are guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5V

bias on the measured terminal. The remaining resistor terminals are left open circuit.

Worst-case supply current consumed when input logic level at 2.4V, standard characteristic of CMOS logic.

PDISS is calculated from (IDD×VDD). CMOS logic level inputs result in minimum power dissipation.

All dynamic characteristics are guaranteed by design and not subject to production test. All dynamic characteristics use VDD=5V.

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