DP83848-HT datasheet(44/81 Pages) TI

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VCC

AN0 = 1

AN1 = 1

AN_EN = 1

DP83848-HT

SLLSEJ7 – FEBRUARY 2015

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Figure 39. AN Strapping and LED Loading Example

8.5.4.2 LED Direct Control

The DP83848 provides another option to directly control any or all LED outputs through the LED direct control

8.5.5 Half Duplex vs Full Duplex

The DP83848 supports both half and full duplex operation at both 10 Mb/s and 100 Mb/s speeds.

Half duplex relies on the CSMA/CD protocol to handle collisions and network access. In half duplex mode, CRS

responds to both transmit and receive activity in order to maintain compliance with the IEEE 802.3 specification.

Since the DP83848 is designed to support simultaneous transmit and receive activity it is capable of supporting

fullduplex switched applications with a throughput of up to 200 Mb/s per port when operating in 100BASE-TX

mode. Because the CSMA/CD protocol does not apply to fullduplex operation, the DP83848 disables its own

internal collision sensing and reporting functions and modifies the behavior of carrier sense (CRS) such that it

indicates only receive activity. This allows a full duplex capable MAC to operate properly.

All modes of operation (100BASE-TX and 10BASE-T) can run either half duplex or full duplex. Additionally, other

than CRS and collision reporting, all remaining MII signaling remains the same regardless of the selected duplex

mode.

It is important to understand that while auto-negotiation with the use of fast link pulse code words can interpret

and configure to full duplex operation, parallel detection can not recognize the difference between full and half

duplex from a fixed 10 Mb/s or 100 Mb/s link partner over twisted pair. As specified in the 802.3u specification, if

a far-end link partner is configured to a forced full duplex 100BASE-TX ability, the parallel detection state

machine in the partner would be unable to detect the full duplex capability of the far-end link partner. This link

segment would negotiate to a half duplex 100BASE-TX configuration (same scenario for 10 Mb/s).

8.5.6 Internal Loopback

The DP83848 includes a loopback test mode for facilitating system diagnostics. The loopback mode is selected

through bit 14 (loopback) of the BMCR. Writing 1 to this bit enables MII transmit data to be routed to the MII

receive outputs. Loopback status may be checked in bit 3 of PHYSTS. While in loopback mode the data will not

be transmitted onto the media. To ensure that the desired operating mode is maintained, Auto-Negotiation

should be disabled before selecting the loopback mode.

8.5.7 BIST

The DP83848 incorporates an internal built-in self test (BIST) circuit to accommodate in-circuit testing or

diagnostics. The BIST circuit can be utilized to test the integrity of the transmit and receive data paths. BIST

testing can be performed with the part in the internal loopback mode or externally looped back using a loopback

cable fixture.

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