MSP34X2G datasheet(21/104 Pages) MICRONAS

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PRELIMINARY DATA SHEET

MSP 34x2G

Micronas

3. Control Interface

3.1. I2C Bus Interface

3.1.1. Device and Subaddresses

The MSP 34x2G is controlled via the I2C bus slave

interface.

The IC is selected by transmitting one of the

MSP 34x2G device addresses. In order to allow up to

three MSP ICs to be connected to a single bus, an

address select pin (ADR_SEL) has been implemented.

With ADR_SEL pulled to high, low, or left open, the

MSP 34x2G responds to different device addresses. A

device address pair is defined as a write address and a

read address (see Table 3–1).

Writing is done by sending the device write address,

followed by the subaddress byte, two address bytes,

and two data bytes. Reading is done by sending the

write device address, followed by the subaddress byte

and two address bytes. Without sending a stop condi-

tion, reading of the addressed data is completed by

sending the device read address and reading two

bytes of data. Refer to Section 3.1.4. for the I2C bus

protocol and to Section 3.4. “Programming Tips” on

page 47 for proposals of MSP 34x2G I2C telegrams.

See Table 3–2 for a list of available subaddresses.

Besides the possibility of hardware reset, the MSP can

also be reset by means of the RESET bit in the CON-

TROL register by the controller via I2C bus.

Due to the internal architecture of the MSP 34x2G, the

IC cannot react immediately to an I2C request. The

typical response time is about 0.3 ms. If the MSP can-

not accept another complete byte of data until it has

performed some other function (for example, servicing

an internal interrupt), it will hold the clock line I2C_CL

LOW to force the transmitter into a wait state. The

positions within a transmission where this may happen

are indicated by “Wait” in Section 3.1.4. The maximum

wait period of the MSP during normal operation mode

is less than 1 ms.

3.1.2. Internal Hardware Error Handling

In case of any internal hardware error (e.g. interruption

of the power supply of the MSP), the MSP’s wait period

is extended to 1.8 ms. After this time period elapses,

the MSP releases data and clock lines.

Indicating and solving the error status:

To indicate the error status, the remaining acknowl-

edge bits of the actual I2C-protocol will be left high.

Additionally, bit[14] of CONTROL is set to one. The

MSP can then be reset via the I2C bus by transmitting

the reset condition to CONTROL.

Indication of reset:

Any reset, even caused by an unstable reset line etc.,

is indicated in bit[15] of CONTROL.

A general timing diagram of the I2C bus is shown in

Fig. 4–21 on page 69.

Table 3–1: I2C Bus Device Addresses

ADR_SEL

Low

High

Left Open

Mode

Write

Read

Write

Read

Write

Read

MSP device address

80hex

81hex

84hex

85hex

88hex

89hex

Table 3–2: I2C Bus Subaddresses

Name

Binary Value

Hex Value

Mode

Function

CONTROL

0000 0000

Read/Write

Write: Software reset of MSP (see Table 3–3)

Read: Hardware error status of MSP

TEST

0000 0001

Write

only for internal use

WR_DEM

0001 0000

Write

write address demodulator

RD_DEM

0001 0001

Write

read address demodulator

WR_DSP

0001 0010

Write

write address DSP

RD_DSP

0001 0011

Write

read address DSP

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