9.10.2

Algorithm

The system can manage the deep sleep state with very low VCC current consumption (500 µA).

The system in deep sleep

•

Monitors the AC line for X-cap discharge and brown-out condition

•

Monitors the burst comparator to detect wake condition

•

Monitors the VCC for data integrity

•

All RAM data are maintained

The device implements two different burst-mode algorithms: the LLC_FB burst or external burst. The first one is

based on just the LLC_FB pin voltage, the second one is based on the external BM comparator on the LLC_AUX

pin that can be driven sensing the output current.

The burst-mode can be programmed to depends either on the LLC_FB pin only, or LLC_AUX pin only, or both.

This third possibility is called hybrid external burst.

In case of the LLC_FB burst-mode, the device enters the sleep mode if the LLC_FB pin voltage goes below a

programmable threshold. The burst switching activity is enabled after the burst comparator is triggered.

The normal switching activity is restored if the time between two bursts is lower than

a programmable threshold. This time defines a precise power level at which the controller exits the burst-mode. In

order to have a faster response to the big load transient the system exits the burst-mode also if the LLC_FB pin

voltage is still above the burst comparator threshold after one burst packet.

In case of the LLC_AUX pin driven burst mode, two types of external burst mode could be defined:

•

Pure external burst mode: only the external BM comparator manages the burst mode entering / exiting;

•

Hybrid external burst mode: if the external BM comparator is high, the system stays out of burst mode while

if the external BM comparator is low, burst mode entering / exiting is managed by the LLC_FB pin settings.

In both external burst mode cases, the burst switching activity is anyway managed by the LLC_FB pin and the

burst comparator.

The PFC and LLC switching activities during the burst-mode are synchronized.

The LLC can perform a burst without the PFC, depending on the system conditions.

9.11

Communication and configuration

The device communicates with an external digital device through a serial interface.

The serial interface uses two dedicated pins with a standard UART protocol. It implements also an I2C protocol

for external E2PROM writing and reading.

The serial interface allows the user to:

•

write the NVM to configure the device in a specific application: 20 bytes are available.

•

write into the RAM for test and SW patch purpose

•

read the NVM content

•

read the RAM content

•

read register content

•

configure the device for specific tests

Based on a specific code into the NVM the serial interface functionality can be reduced for security reasons.

9.11.1

Monitor

Some internal data can be provided to an external digital device trough the UART interface for monitoring

purposes.

9.11.2

Black box

Black box data are written into the external E2PROM during the normal operation.

9.11.3

Patches

SW patches (if necessary) are uploaded by the device from the external E2PROM at the startup.

Maximum patch size is 2.5 kB.

STNRG011

Communication and configuration

DS12075 - Rev 4

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