5

Pin function

Table 3. Pin function detailed description

No.

Name

Function

1

BOOT

High-side gate-drive floating supply voltage.

The bootstrap capacitor is connected between this pin and FGND.

A fast diode has to be connected from this pin and VCC to guarantee recharge of the bootstrap capacitor.

2

HVG

High-side gate-drive output.

The driver is capable of 0.5 A source and 0.75 A sink peak current (minimum values) to drive the upper

MOSFET of the half-bridge leg.

A resistor internally connected to FGND ensures that the pin is never floating.

3

FGND

High-side gate-drive floating ground.

It is the return path for the high-side gate-drive current.

Layout carefully the connection of this pin to avoid too large spikes below ground.

4

N.C.

High-voltage spacer.

The pin is not internally connected to isolate the high-voltage section and ease compliance with safety

regulations (creepage distance) on the PCB.

5

LVG

Low-side gate-drive output.

The driver is capable of 0.5 A source and 0.75 A sink peak current (minimum values) to drive the lower

MOSFET of the half-bridge leg.

The pin is actively pulled to GND during UVLO.

6

TX

TX pin for UART/SDA pin for I2C interface

7

RX

RX pin for UART/SCL pin for I2C interface

8

LLC_CS

LLC tank current sensing input. A voltage proportional to the tank current (usually obtained with a capacitive

divider) has to be applied to this pin.

The information is used for zero-crossing detection (required by time-shift algorithm), the first and second

level OCP.

9

LLC_AUX

LLC_AUX is connected to a divider sensing the auxiliary voltage from the LLC transformer. The LLC OVP

detection is active on this pin.

10

LLC_FB

The voltage from this pin is used as the LLC feedback voltage. It has to be connected to the feedback

phototransistor collector and a pull-up resistor to VCORE.

11 PFC_ZCD

PFC ZCD input, connected to the PFC AUX winding through a resistor divider detecting the PFC inductor

demagnetization.

12

PFC_CS

Current sense input for PFC.

The current flowing in the MOSFET is sensed through a resistor, and the resulting voltage is applied to this

pin.

After GD turns on, a first voltage threshold cross allows enhanced COT control implementation. A second

level can be detected for overcurrent protection.

13

PFC_FB

Input for PFC output voltage. It is used for closing the PFC loop and OVP protection. It has to be connected

with a voltage divider to the bulk capacitor. If the early warning feature is enabled this pin is brought to 5 V

when the EW pulse is released.

14

VCORE

Internal VCORE bypass capacitor connection.

15

SGND

Signal ground. Reference ground for analog signals.

16

PGND

Power ground. Current return for the PFC gate-driver and the low-side gate-driver of the half- bridge. Keep

the PCB trace that goes from this pin to the sources of the PFC and the low-side MOSFETs separate from

the trace that collects the grounding of the bias components.

17

PFC_GD

PFC gate-driver output.

The output stage is able to drive power MOSFETs, it is capable of 0.7 A source current and

STNRG011

Pin function

DS12075 - Rev 4

page 6/31