AAT2500 datasheet(19/26 Pages) ANALOGICTECH

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Thermal Calculations

There are three types of losses associated with the

AAT2500 step-down converter: switching losses,

conduction losses, and quiescent current losses.

Conduction losses are associated with the RDS(ON)

characteristics of the power output switching

devices. Switching losses are dominated by the

gate charge of the power output switching devices.

At full load, assuming continuous conduction mode

(CCM), a simplified form of the step-down convert-

er and LDO losses is given by:

IQBUCK is the step-down converter quiescent cur-

rent and IQLDO is the LDO quiescent current. The

term tsw is used to estimate the full load step-down

converter switching losses.

For the condition where the buck converter is in

dropout at 100% duty cycle, the total device dissi-

pation reduces to:

Since RDS(ON), quiescent current, and switching

losses all vary with input voltage, the total losses

should be investigated over the complete input

voltage range.

Given the total losses, the maximum junction tem-

perature can be derived from the

θJA for the

TDFN/STDFN33-12 package which is 50°C/W.

PCB Layout

The following guidelines should be used to ensure

a proper layout.

1. The input capacitor C2 should connect as

closely as possible to VP and PGND, as shown

in Figure 4.

2. The output capacitor and inductor should be

connected as closely as possible. The connec-

tion of the inductor to the LX pin should also be

as short as possible.

3. The feedback trace should be separate from

any power trace and connect as closely as

possible to the load point. Sensing along a

high-current load trace will degrade DC load

regulation. If external feedback resistors are

used, they should be placed as closely as pos-

sible to the FB pin. This prevents noise from

being coupled into the high impedance feed-

back node.

4. The resistance of the trace from the load return

to GND should be kept to a minimum. This will

help to minimize any error in DC regulation due

to differences in the potential of the internal sig-

nal ground and the power ground.

5. For good thermal coupling, PCB vias are

required from the pad for the TDFN/STDFN pad-

dle to the ground plane. The via diameter should

be 0.3mm to 0.33mm and positioned on a

1.2mm grid.

6. LDO bypass capacitor (C5) should be connected

directly between pins 7 (BYP) and 8 (GND)

TJ(MAX) = PTOTAL · ΘJA + TAMB

PTOTAL = IOBUCK2 · RDSON(HS) + IOLDO · (VIN - VOLDO)

+ (IQBUCK + IQLDO) · VIN

PTOTAL

IOBUCK2 · (RDSON(HS) · VOBUCK + RDSON(LS) · [VIN - VOBUCK])

VIN

+ (tsw · F · IOBUCK + IQBUCK + IQLDO) · VIN + IOLDO · (VIN - VOLDO)

AAT2500

1MHz Step-Down Converter/LDO Regulator

2500.2006.05.1.16

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