AAT2500 datasheet(16/26 Pages) ANALOGICTECH

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AAT2500

1MHz Step-Down Converter/LDO Regulator

2500.2006.05.1.16

Manufacturer's specifications list both the inductor

DC current rating, which is a thermal limitation, and

the peak current rating, which is determined by the

saturation characteristics. The inductor should not

show any appreciable saturation under normal load

conditions. Some inductors may meet the peak and

average current ratings yet result in excessive loss-

es due to a high DCR. Always consider the losses

associated with the DCR and its effect on the total

converter efficiency when selecting an inductor.

The 4.7µH CDRH3D16 series inductor selected

from Sumida has a 105m

Ω DCR and a 900mA DC

current rating. At full load, the inductor DC loss is

17mW which gives a 2.8% loss in efficiency for a

400mA, 1.5V output.

Input Capacitor

Select a 4.7µF to 10µF X7R or X5R ceramic capac-

itor for the input. To estimate the required input

capacitor size, determine the acceptable input rip-

ple level (VPP) and solve for C. The calculated

value varies with input voltage and is a maximum

when VIN is double the output voltage.

Always examine the ceramic capacitor DC voltage

coefficient characteristics when selecting the prop-

er value. For example, the capacitance of a 10µF,

6.3V, X5R ceramic capacitor with 5.0V DC applied

is actually about 6µF.

The maximum input capacitor RMS current is:

The input capacitor RMS ripple current varies with

the input and output voltage and will always be less

than or equal to half of the total DC load current.

for VIN = 2 x VOBUCK

The term

appears in both the

input voltage ripple and input capacitor RMS cur-

rent equations and is a maximum when VOBUCK is

twice VIN. This is why the input voltage ripple and

the input capacitor RMS current ripple are a maxi-

mum at 50% duty cycle.

The input capacitor provides a low impedance loop

for the edges of pulsed current drawn by the

AAT2500. Low ESR/ESL X7R and X5R ceramic

capacitors are ideal for this function. To minimize

stray inductance, the capacitor should be placed as

closely as possible to the IC. This keeps the high

frequency content of the input current localized,

minimizing EMI and input voltage ripple.

The proper placement of the input capacitor (C2)

can be seen in the evaluation board layout in

Figure 3.

A laboratory test set-up typically consists of two

long wires running from the bench power supply to

the evaluation board input voltage pins. The induc-

tance of these wires, along with the low-ESR

ceramic input capacitor, can create a high Q net-

work that may affect converter performance. This

problem often becomes apparent in the form of

excessive ringing in the output voltage during load

transients. Errors in the loop phase and gain meas-

urements can also result.

Since the inductance of a short PCB trace feeding

the input voltage is significantly lower than the

power leads from the bench power supply, most

applications do not exhibit this problem.

⎛⎞

· 1 -

⎝⎠

VOBUCK

VIN

VOBUCK

VIN

IOBUCK

RMS(MAX)

⎛⎞

· 1 -

= D · (1 - D) =

0.52 =

⎝⎠

VOBUCK

VIN

VOBUCK

VIN

⎛⎞

IRMS = IOBUCK ·

· 1 -

⎝⎠

VOBUCK

VIN

VOBUCK

VIN

CIN(MIN) =

⎛⎞

- ESR

4 · FS

⎝⎠

VPP

IOBUCK

⎛⎞

· 1 -

for VIN = 2 × VOBUCK

⎝⎠

VOBUCK

VIN

VOBUCK

VIN

⎛⎞

· 1 -

⎝⎠

VOBUCK

VIN

CIN =

VOBUCK

VIN

⎛⎞

- ESR

⎝⎠

VPP

IOBUCK

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