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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PI7C9X760 датащи(PDF) 32 Page - Diodes Incorporated |
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PI7C9X760 датащи(HTML) 32 Page - Diodes Incorporated |
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32 / 53 page  32 www.diodes.com April 2019 Diodes Incorporated PI7C9X760 Document Number DS40305 Rev 6-2 A product Line of Diodes Incorporated PI7C9X760 Offset 07H: Scratch Pad Register (SPR). Accessible when LCR[7]=0 and MCR[2]=0. Default=FF Bit Type Description [7:0] RW This is 8-bit general purpose register for the user to store temporary data. The content is preserved during sleep mode. Note: It is reset only when Power-On-Reset. Offset 07H: Trigger Level Register (TLR). Accessible when EFR[4]=1 and MCR[2]=1. Default=00 Bit Type Description [7:4] RW RX FIFO Trigger level. When the number of characters received in RX FIFO is greater than or equal to the value (decimal value of TLR[7:4] multiplied by 4), a Receive Data Ready interrupt is generated. If TLR[7:4]=0x0, then the RX FIFO Trigger Level is the value selected by FCR[7:6] [3:0] RW TX FIFO Trigger level. When the number of available space in TX FIFO is greater than or equal to the value (decimal value of TLR[3:0] multiplied by 4), a Transmit Ready interrupt is generated. If TLR[3:0]=0x0, then the TX FIFO Trigger Level is the value selected by FCR[5:4] Offset 07H: XOFF2 character Register (XOFF2). Accessible when LCR=0xBF and SFREN!=0x5A. Default=00 Bit Type Description [7:0] RW XOFF2 character Note: It is reset only when Power-On-Reset. Offset 08H: Transmit FIFO Level Register (TXLVL). Accessible when SFR[2]=0. Default=40 Bit Type Description [7:0] RO This register reports the number of spaces available in the TX FIFO. Offset 09H: Receiver FIFO Level Register (RXLVL). Accessible when SFR[2]=0. Default=00 Bit Type Description [7:0] RO This register reports the number of character available in the RX FIFO. Offset 0AH: GPIO Direction Register (IODir). Default=00 Bit Type Description [7:0] RW This register program the direction of the GPIO pins. 0 = set GPIO pin as input 1 = set GPIO pin as output Offset 0BH: GPIO State Register (IOState). Default=FF Bit Type Description [7:0] RW This register reports the state of all GPIO pins during read and writes to any GPIO that is an output 0 = set output pin LOW 1 = set output pin HIGH Configuration Registers cont.. |
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