33975 datasheet(25/32 Pages) FREESCALE

25 / 32 page

Analog Integrated Circuit Device Data

Freescale Semiconductor

33975

TYPICAL APPLICATIONS

OPERATIONAL MODES

Multiple 33975 devices may be used in a module system.

SPI control may be done in parallel or serial. However when

parallel mode is used, each device is addressed

independently (refer to MCU Interface Description, page 13).

Therefore when sending the sleep command, one device will

enter sleep before the other. For multiple devices in a system,

it is recommended that the devices are controlled in serial (S0

from first device is connected to SI of second device). With

two devices, 48 clock pulses are required to shift data in.

When the WAKE feature is used to enable the power supply,

both WAKE terminals should be connected to the enable

terminal on the power supply. The INT terminals may be

connected to one interrupt terminal on the MCU or may have

their own dedicated interrupt to the MCU.

The transition from Normal to Sleep mode is done by

sending the sleep command. With the devices connected in

serial and the sleep command sent, both will enter Sleep

mode on the rising edge of CS. When Sleep mode is entered,

the WAKE terminal will be logic [1]. If either device wakes up,

the WAKE terminal will transition low, waking the other

device.

A condition exists where the MCU is sending the sleep

command (CS logic [0]) and a switch input changes state.

With this event the device that detects this input will not

transition to Sleep mode, while the second device will enter

Sleep mode. In this case two switch status commands must

be sent to receive accurate switch status data. The first

switch status command will wake the device in Sleep mode.

Switch status data may not be valid from the first switch

status command because of the time required for the input

voltage to rise above the 4.0 V input comparator threshold.

This time is dependant on the impedance of SGn or SPn

node. The second switch status command will provide

accurate switch status information. It is recommended that

software wait 10 ms to 20 ms between the two switch status

commands, allowing time for switch input voltages to

stabilize. With all switch states acknowledged by the MCU,

the sleep sequence may be initiated. All parameters for Sleep

mode should be updated prior to sending the sleep

command.

The 33975 IC has an internal 5.0 V supply from the VPWR

terminal. A POR circuit monitors the internal 5.0 V supply. In

the event of transients on the VPWR terminal, an internal

reset may occur. Upon reset the 33975 will enter Normal

mode with the internal registers as defined in Table 15,

page 18. Therefore it is recommended that the MCU

periodically update all registers internal to the IC.

USING THE WAKE FEATURE

The 33975 provides a WAKE output and wake-up input

designed to control an enable terminal on system power

supply. While in the Normal mode, the WAKE output is low,

enabling the power supply. In the Sleep mode, the WAKE

terminal is high, disabling the power supply. The WAKE

terminal has a passive pull-up to the internal 5.0 V supply but

may be pulled up through a resistor to VPWR supply (see

Figure 16, page 26).

When the WAKE output is not used the terminal should be

pulled up to the VDD supply through a resistor as shown in

Figure 15, page 26).

During the Sleep mode, a switch closure will set the WAKE

terminal low, causing the 33975 to enter the Normal mode.

The power supply will then be activated, supplying power to

the VDD terminal and the microprocessor and the 33975. The

microprocessor can determine the source of the wake-up by

reading the interrupt flag.

COST AND FLEXIBILITY

Systems requiring a significant number of switch

interfaces have many discrete components. Discrete

components on standard PWB consume board space and

must be checked for solder joint integrity. An integrated

approach reduces solder joints, consumes less board space,

and offers wider operating voltage, analog interface

capability, and greater interfacing flexibility.

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