LT4293 datasheet(32/44 Pages) AD

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LTC9101-2/LTC9102

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

For information on serial bus usage and device configura-

tion and status, refer to the LTC9101-2NDASI Software

Interface guide. Contact Analog Devices to request

this document.

ISOLATION REQUIREMENTS

IEEE 802.3 Ethernet specifications require that network

segments (including PoE circuitry) be electrically isolated

from the chassis ground of each network interface device.

However, network segments are not required to be iso-

lated from each other, provided that the segments are

connected to devices residing within a single building on

a single power distribution system.

If the PSE is part of a larger system, contains additional

external non-Ethernet ports, or must be referenced to pro-

tective ground for some other reason, the PoE subsystem

must be electrically isolated from the rest of the system.

The LTC9101-2/LTC9102 chipset simplifies PSE isolation

by allowing the LTC9101-2 chip to reside on the non-

isolated side. There it can receive power from the main

logic supply and connect directly to the I2C/SMBus bus.

In this case, the SDAIN and SDAOUT pins can be tied

together and will act as a standard I2C/SMBus SDA pin.

Isolation between the LTC9101-2 and LTC9102 is imple-

mented using a proprietary transformer-based commu-

nication protocol. Additional details are provided in the

High-Speed Data Isolation section of this data sheet.

For simple devices, such as unmanaged PoE switches,

the isolation requirement can be met by using an isolated

main power supply for the entire device. This strategy

can be used if the device has no electrically conducting

ports other than twisted-pair Ethernet. The LTC9101-2

may directly connect to the LTC9102s in the above cir-

cumstances, or if the system already provides isolation.

EXTERNAL COMPONENT SELECTION

Power Supplies

The LTC9101-2/LTC9102 requires two supply voltages to

operate. VDD requires 3.3V (nominally) relative to DGND.

SERIAL DIGITAL INTERFACE

Overview

The LTC9101-2 communicates with the host using a

standard SMBus/I2C 2-wire interface. The LTC9101-2 is a

slave-only device, and communicates with the host master

using standard SMBus protocols. Interrupts are signaled

to the host via INT. The timing diagrams (Figure 5 through

Figure 9) show typical communication waveforms and

their timing relationships. More information about the

SMBus data protocols can be found at www.smbus.org.

Bus Addressing

The LTC9101-1’s primary 7-bit serial bus address is

01A4A3A2A10b, with bits 4:1 set by AD[4:1] respectively.

See Table 4 for device configuration options. Depending on

device configuration, up to 12 I2C addresses will be popu-

lated from the I2C base address upwards. All LTC9101-2s

also respond to the broadcast address 1111111b, allow-

ing the host to write the same command (typically con-

figuration commands) to multiple LTC9101-2s in a single

transaction. If the LTC9101-2 is asserting INT, it will also

respond to the alert response address (0001100b) per the

SMBus specification.

Each LTC9101-2/LTC9102 is logically composed of mul-

tiple four port groups, known as quads, each packed

into a single I2C address. See Device Configuration sec-

tion for details. For example, if CFG[1:0] is set to 00,

an LTC9101-2 is configured as a 12-port device when

attached to an LTC9102 (see Table 4). This configuration

requires consecutive I2C addresses, with quad offset 0

starting at the I2C base address.

Interrupts and SMBAlert

Most port events can be configured to trigger an inter-

rupt, asserting INT and alerting the host to the event. This

removes the need for the host to poll the LTC9101-2,

minimizing serial bus traffic and conserving host CPU

cycles. Multiple LTC9101-2s can share a common INT

line, with the host using the SMBAlert protocol (ARA) to

determine which LTC9101-2 caused an interrupt.

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