Note 9: Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for this device,

therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Figure 2. For relationship between Gain Error and Full-Scale Error, see Specification

Definitions for Gain Error.

Note 10: The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.65 pF differential and 0.95 pF each pin to ground

are isolated from the die capacitances by lead and bond wire inductances.

Note 11: This parameter is guaranteed by design and is not tested in production.

Note 12: This parameter is guaranteed by design and/or characterization and is not tested in production.

Note 13: The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated from the die

capacitances by lead and bond wire inductances.

Note 14: Each of the two converters of the ADC083000 has two LVDS output buses, which each clock data out at one half the sample rate. The data at each bus

is clocked out at one half the sample rate. The second bus (D0 through D7) has a pipeline latency that is one Input Clock cycle less than the latency of the first bus

(Dd0 through Dd7).

Specification Definitions

APERTURE (SAMPLING) DELAY is that time required after

the fall of the clock input for the sampling switch to open. The

Sample/Hold circuit effectively stops capturing the input sig-

nal and goes into the “hold” mode the aperture delay time

(t

APERTURE JITTER (t

from sample to sample. Aperture jitter shows up as input

noise.

Bit Error Rate (B.E.R.) is the probability of error and is

defined as the probable number of errors per unit of time

divided by the number of bits seen in that amount of time. A

B.E.R. of 10

about every four (4) years.

CLOCK DUTY CYCLE is the ratio of the time that the clock

wave form is at a logic high to the total time of one clock

period.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of

the maximum deviation from the ideal step size of 1 LSB.

Measured at 3 GSPS with a ramp input.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE

BITS) is another method of specifying Signal-to-Noise and

Distortion Ratio, or SINAD. ENOB is defined as (SINAD −

1.76) / 6.02 and says that the converter is equivalent to a

perfect ADC of this (ENOB) number of bits.

FULL POWER BANDWIDTH (FPBW) is a measure of the

frequency at which the reconstructed output fundamental

drops 3 dB below its low frequency value for a full scale

input.

GAIN ERROR is the deviation from the ideal slope of the

transfer function. It can be calculated from Offset and Full-

Scale Errors:

Positive Gain Error = Offset Error − Positive Full-Scale

Error

Negative Gain Error = −(Offset Error − Negative Full-

Scale Error)

Gain Error = Negative Full-Scale Error − Positive Full-

Scale Error = Positive Gain Error + Negative Gain Error

INTEGRAL NON-LINEARITY (INL) is a measure of the

deviation of each individual code from a straight line through

the input to output transfer function. The deviation of any

given code from this straight line is measured from the

center of that code value. The best fit method is used.

INTERMODULATION DISTORTION (IMD) is the creation of

additional spectral components as a result of two sinusoidal

frequencies being applied to the ADC input at the same time.

It is defined as the ratio of the power in the second and third

order intermodulation products to the power in one of the

original frequencies. IMD is usually expressed in dBFS.

LSB (LEAST SIGNIFICANT BIT) is the bit that has the

smallest value or weight of all bits. This value is

V

n

where V

or 870 mV as set by the FSR input and "n" is the ADC

resolution in bits, which is 8 for the ADC083000.

LVDS DIFFERENTIAL OUTPUT VOLTAGE (V

absolute value of the difference between the V

outputs; each measured with respect to Ground.

LVDS OUTPUT OFFSET VOLTAGE (V

between the D+ and D- pins output voltage; ie., [(V

V

MISSING CODES are those output codes that are skipped

and will never appear at the ADC outputs. These codes

cannot be reached with any input value.

MSB (MOST SIGNIFICANT BIT) is the bit that has the

largest value or weight. Its value is one half of full scale.

NEGATIVE FULL-SCALE ERROR (NFSE) is a measure of

how far the last code transition is from the ideal 1/2 LSB

above a differential −435 mV with the FSR pin high, or 1/2

LSB above a differential −325 mV with the FSR pin low. For

the ADC083000 the reference voltage is assumed to be

ideal, so this error is a combination of full-scale error and

reference voltage error.

OFFSET ERROR (V

scale point is from the ideal zero voltage differential input.

Offset Error = Actual Input causing average of 8k

samples to result in an average code of 127.5.

OUTPUT DELAY (t

of DCLK before the data update is present at the output pins.

20193246

FIGURE 1.

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