ADC083000 datasheet(21/33 Pages) NSC

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1.0 Functional Description (Continued)

power consumption. If the LVDS lines are long and/or the

system in which the ADC083000 is used is noisy, it may be

necessary to tie the OutV pin high.

The LVDS data output have a typical common mode voltage

of 800mV when the V

BG pin is unconnected and floating.

This common mode voltage can be increased to 1.2V by

tying the V

BG pin to VA if a higher common mode is required.

1.1.7 Power Down

The ADC083000 is in the active state when the Power Down

pin (PD) is low. When the PD pin is high, the device is in the

power down mode. In this power down mode the data output

pins (positive and negative) including DCLK+/- and OR +/-

are put into a high impedance state and the devices power

consumption is reduced to a minimal level.

If the PD input is brought high while a calibration is running,

the device will not go into power down until the calibration

sequence is complete. However, if power is applied and PD

is already high, the device will not begin the calibration

sequence until the PD input goes low. If a manual calibration

is requested while the device is powered down, the calibra-

tion will not begin at all. That is, the manual calibration input

is completely ignored in the power down state.

1.2 NORMAL/EXTENDED CONTROL

The ADC083000 may be operated in one of two modes. In

the simpler standard control mode, the user affects available

configuration and control of the device through several con-

trol pins. The "extended control mode" provides additional

configuration and control options through a serial interface

and a set of 6 registers. The two control modes are selected

with pin 14 (FSR/ECE: Extended Control Enable). The

choice of control modes is required to be a fixed selection

and is not intended to be switched dynamically while the

device is operational.

Table 2 shows how several of the device features are af-

fected by the control mode chosen.

TABLE 2. Features and modes

Feature

Normal Control Mode

Extended Control Mode

SDR or DDR Clocking

Selected with pin 4

Selected with DE bit in the

Configuration Register

DDR Clock Phase

Not Selectable (0˚ Phase Only)

Selected with DCP bit in the

Configuration Register. See Section

1.4 REGISTER DESCRIPTION

SDR Data transitions with rising or

falling DCLK edge

Selected with pin 4

Selected with the OE bit in the

Configuration Register

LVDS output level

Selected with pin 3

Selected with the OV bit (9)in the

Configuration Register

Power-On Calibration Delay

Delay Selected with pin 127

Short delay only.

Full-Scale Range

Options (650 mV

P-P or 870 mVP-P)

selected with pin 14. Selected range

applies to both channels.

Up to 512 step adjustments over a

nominal range of 560 mV to 840 mV.

Selected using registers 3H.

Input Offset Adjust

Not possible

Separate ±45 mV adjustments in 512

steps using registers 2h.

Sampling Clock Phase Adjustment

The Clock Phase is adjusted

automatically

The clock phase can be adjusted

manually through the Coarse & Fine

registers (Eh and Dh).

Test Pattern

Not Possible

A test pattern can be made present at

the data outputs by programming

Resistor Trim Disable

Not possible

The DCLK outputs will continuously be

present when bit 5 is set 1b in register

1h.

Selectable Output Demultiplexer

Not possible

If the device is set in DDR, the output

can be programmed to be 1:2

demultiplexed. Bit 0 in register 1h is

set 1b, this selects 1:2 demultiplex. If

bit 0 is 0b, this selects 1:4 demultiplex.

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