TDA7577BLVPD datasheet(28/43 Pages) STMICROELECTRONICS

номер детали	TDA7577BLVPD

подробное описание детали	2 x 75 W dual-bridge power amplifier with I2C complete diagnostics and

PDF	43 Pages

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производитель	STMICROELECTRONICS [STMicroelectronics]

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28 / 43 page

I2C bus interface

TDA7577BLV

28/43

DocID025375 Rev 5

I2C bus interface

Data transmission from microprocessor to the TDA7577BLV and vice versa takes place

through the 2 wires I2C bus interface, consisting of the two lines SDA and SCL (pull-up

resistors to positive supply voltage must be connected).

9.1

Data validity

As shown by Figure 37, the data on the SDA line must be stable during the high period of

the clock.

The HIGH and LOW state of the data line can only change when the clock signal on the SCL

line is LOW.

9.2

Start and stop conditions

As shown by Figure 38 a start condition is a HIGH to LOW transition of the SDA line while

SCL is HIGH.

The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.

9.3

Byte format

Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an

acknowledge bit. The MSB is transferred first.

9.4

Acknowledge

The transmitter(*) puts a resistive HIGH level on the SDA line during the acknowledge clock

pulse (see Figure 39). The receiver(**) has to pull-down (LOW) the SDA line during the

acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse.

(*) Transmitter

= master (μP) when it writes an address to the TDA7577BLV

= slave (TDA7577BLV) when the μP reads a data byte from TDA7577BLV

(**) Receiver

= slave (TDA7577BLV) when the μP writes an address to the TDA7577BLV

= master (μP) when it reads a data byte from TDA7577BLV

Figure 37. Data validity on the I2C bus

TDA7577BLVPD датащи(PDF) 28 Page - STMicroelectronics