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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TDA7577BLVPD датащи(PDF) 23 Page - STMicroelectronics |
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TDA7577BLVPD датащи(HTML) 23 Page - STMicroelectronics |
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23 / 43 page  DocID025375 Rev 5 23/43 TDA7577BLV 1 Ω load capability setting 42 5 1 Ω load capability setting It is possible to drive 1 Ω load paralleling the outputs into a single channel. In order to implement this feature, outputs should be connected as follows: OUT1+ shorted to OUT2+ OUT1- shorted to OUT2-. It is recommended to minimize the impedance on the board between OUT2 and the load in order to minimize THD distortion. It is also recommended to control the maximum mismatch impedance between VCC pins (PIN21/PIN22 respect to PIN33/PIN34) and between PWGND pins (PIN24/PIN25 respect to PIN30/PIN31), mismatch that must not exceed a value of 20 mΩ With 1Ω feature settled the active input is IN2 (PIN17 and PIN18), therefore IN1 pins should be let floating. It is possible to set the load capability acting on 1 Ω pin as follows: 1 Ω PIN < 1.2V: two channels mode (for a minimum load of 2 Ω) 1 Ω PIN > 2.6V: one channel mode (for 1 Ω load). It is to remember that 1 Ω function is a hardware selection. Therefore it is recommended to leave 1 Ω pin floating or shorted to GND to set the two channels mode configuration, or to short 1 Ω pin to VCC to set the one channel (1 Ω) configuration. |
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