L9918 datasheet(32/109 Pages) STMICROELECTRONICS

32 / 109 page

Symbol

Parameter

Notes

Min.

Typ.

Max.

Unit

VBusdom

Receiver dominant state

0.4 * B+

Vth_rec

Receiver threshold voltage dominant to

recessive state)

0.5 * B+

0.55 * B+

0.6 * B+

VBusrec

Receiver recessive state

0.6 * B+

VLIN_CNT

Centering

VLIN_CNT = (Vth_dom + Vth_rec)/2

0.475 * B

0.5 * B+

0.525 * B

Vth_HYS

Receiver hysteresis Vth_HYS = Vth_rec -

Vth_dom

0.07 * B+

0.1 * B+

0.175 * B

tBFS

Accuracy of the byte field detection

2/16

Bit

time

tEBS

Earliest bit sample time tEBS ≤ tLBS

7/16

Bit

time

tLBS

Latest bit sample time tLBS ≥ tEBS

8/16

Bit

time

tWUDEL

Time for valid LIN communication after

Wake up event

208

μs

VTHwkup

Activation threshold for wake-up

comparator

1.0

1.5

VTHwkdwn

Activation threshold for wake-up

comparator

(B+) - 3.5

(B+) - 2.5

(B+) - 1.5

tLINBUS

LIN Bus Wake-up Dominant Filter time

Sleep mode; edge: rec-dom

μs

tdom_LIN

LIN Bus Wake-up Dominant Filter time

Sleep mode; edge: rec-dom-rec

μs

Duty cycle D1 Valid for 20 kBaud

THREC(max) = 0.744 * VB+,

THDOM(max) = 0.581 * VB+,

VB+=7.0 V to 18 V,

tBIT = 50 μs,

D1 = tBUS_rec(min) / (2*tBIT) (1)

0.396

Duty cycle D2 Valid for 20 kBaud

THREC(min) = 0.422 x VB+,

THDOM(min) = 0.284 x VB+,

VB+ = 7.6 V to 18 V,

tBIT = 50 μs,

D2 = tBUS − rec(max) / (2tBIT) (1)

0.581

Duty cycle D3 Valid for 10.4 kBaud

THREC(max) = 0.778 x VB+,

THDOM(max) = 0.616 x VB+,

VB+ = 7.0 V to 18 V,

tBIT = 96μs,

D3 = tBUS − rec(min) / (2tBIT) (1)

0.417

Duty cycle D4 Valid for 10.4 kBaud

THREC(min) = 0.389 x VB+,

THDOM(min) = 0.251 x VB+,

VB+ = 7.6 V to 18 V,

tBIT = 96μs,

D4 = tBUS − rec(max) / (2tBIT) (1)

0.59

L9918

LIN Physical layer

DS13000 - Rev 2

page 32/109

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