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TPS613761 датащи(PDF) 21 Page - Texas Instruments |
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TPS613761 датащи(HTML) 21 Page - Texas Instruments |
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21 / 27 page ![]() 9.2.3 Application Curves (continued) Time Scale 200 s/div VOUT(AC) 300mV/div IOUT 500mA/div VIN = 3.3 V VOUT = 12 V Figure 9-8. Load Transient (IOUT = 0.1 to 0.5 A) Time Scale 200 s/div VOUT(AC) 300mV/div IOUT 500mA/div VIN = 8.4 V VOUT = 12 V Figure 9-9. Load Transient (IOUT = 0.1 to 0.5 A) Time Scale 200 s/div VOUT(AC) 200mV/div IL 1A/div VIN 3V/div VOUT = 12 V IOUT = 0.5 A Figure 9-10. Line Transient (VIN = 3.3 V to 8.4 V) 9.3 Power Supply Recommendations The device is designed to operate from an input voltage supply range between 2.9 V to 23 V. This input supply must be well regulated. If the input supply is located more than a few inches from the converter, additional bulk capacitance can be required in addition to the ceramic bypass capacitors. A typical choice is an electrolytic or tantalum capacitor with a value of 47 μF. 9.4 Layout 9.4.1 Layout Guidelines As for all switching power supplies, especially those running at high switching frequency and high current, layout is an important design step. If the layout is not carefully done, the regulator can suffer from instability and noise problems. To maximize efficiency, switch rise and fall times are very fast. To prevent radiation of high-frequency noise (for example, EMI), proper layout of the high-frequency switching path is essential. Minimize the length and area of all traces connected to the SW pin, and always use a ground plane under the switching regulator to minimize interplane coupling. The input capacitor needs to be close to the VIN pin and PGND pin in order to reduce the Iinput supply ripple. The power paths of SW, D1,output capacitor and PGND should be as small as possible, in order to reduce parasitic inductance. The layout should also be done with well consideration of the thermal as this is a high power density device. The VP, SW, VOUT and PGND pins that improves the thermal capabilities of the package should be soldered with the large polygon, using thermal vias underneath the SW pin could improve thermal performance. www.ti.com TPS61376 SLVSGQ1A – JANUARY 2022 – REVISED SEPTEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TPS61376 |
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