STA8090EXGA datasheet(24/42 Pages) STMICROELECTRONICS

24 / 42 page

General description

STA8090EXGA

24/42

DS11733 Rev 3

EFT features



Programmable prescaler: fAPB divided from 1 to 256, prescaler register (0 to 255)

value +1.



Overflow status flag and maskable interrupts.



Output compare functions with:

–

2 dedicated 16-bit registers

–

2 dedicated programmable signals

–

2 dedicated status flags

–

2 dedicated interrupt flags



Input capture functions with:

–

2 dedicated 16-bit registers

–

2 dedicated active edge selection signals

–

2 dedicated status flags

–

2 dedicated interrupt flags



Pulse Width Modulation mode (PWM).



One Pulse Mode (OPM).



PWM input mode.



Timer global interrupt (5 internally ORed)

–

ICIA: timer input capture A interrupt

–

ICIB: timer input capture B interrupt

–

OCIA: timer output compare A interrupt

–

OCIB: timer output compare B interrupt

–

TOI: timer overflow interrupt

3.4.3

SSP

The SSP is a master interface for synchronous serial communication with peripheral

devices that have Motorola SPI.

The SSP performs serial-to-parallel conversion on data received from a peripheral device

on SPI_DI pin, and parallel-to-serial conversion on data written by CPU for transmission on

SPI_DO pin. The transmit and receive paths are buffered with internal FIFO memories

allowing up to 32 x 32-bit values to be stored independently in both transmit and receive

modes. FIFOs may be burst-loaded or emptied by the system processor or DMA, from one

to eight words per transfer. Each 32-bit word from the system fills one entry in FIFO.

The SSP includes a programmable bit rate clock divider and prescaler to generate the serial

output clock SSPCLK from the on-chip clock. One combined interrupt is delivered, which is

asserted from several internal maskable events.

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