L99H02 datasheet(22/51 Pages) STMICROELECTRONICS

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Electrical specifications

L99H02

22/51

DS12547 Rev 6

Figure 6. SPI - transfer timing diagram

Table 21. DO timing

Item

Symbol

Parameter

Test condition

Min.

Typ.

Max. Unit

21.1

tr DO

DO rise time

CL = 100 pF;

Iload =-1mA

—80

140

21.2

tf DO

DO fall time

CL = 100 pF; Iload =1mA

—

100

21.3

ten DO tri L

DO enable time from

tristate to low-level

CL = 100 pF; Iload =1mA;

pull-up load to VCC

—100

250

21.4

tdis DO L tri

DO disable time from

low-level to tristate

CL = 100 pF; Iload =4mA;

pull-up load to VCC

—380

450

21.5 ten DO tri H

DO enable time from

tristate to high-level

CL = 100 pF;

Iload = -1 mA; pull-down load

to GND

—100

250

21.6 tdis DO H tri

DO disable time from

high-level to tristate

CL = 100 pF;

Iload = -4 mA; pull-down load

to GND

—380

450

21.7

td DO

DO delay time

VDO <0.3 VCC;

VDO >0.7 VCC; CL = 100 pF

—50

250

Table 22. EN, CSN timing

Item

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

22.3

tCSN_HI,min

CSN HI time, active

mode: the min high time

between two independent

SPI commands.

Transfer of SPI-

command to input

2µs

time

CSN high to low: DO enabled

actual data

DI: data will be accepted on the rising edge of CLK signal

new data

CSN

CLK

Input data

DO: data will change on the falling edge of CLK signal

status information

fault bit

CSN low to high: actual data is

transferred

old data

actual data

GADG161020201118RI

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