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RZ/N2L датащи(PDF) 76 Page - Renesas Technology Corp

номер детали RZ/N2L
подробное описание детали  RZ Arm-based High-end 32 & 64-bit MPUs
PDF  127 Pages
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производитель  RENESAS [Renesas Technology Corp]
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RZ/N2L датащи(HTML) 76 Page - Renesas Technology Corp

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2.5.5.6
POEG Timing
Table 2.30
POEG timing
Parameter
Symbol
Min.
Max.
Unit*1
Reference figure
POEG
GTETRGn input pulse width (n = A to D)
tPOEGW
2.5
—
tPHcyc
Figure 2.49
Output
disable time
Input level detection of the
GTETRGn pin (via flag)
tPOEGDI
—
3 × PCLKH
+ 0.1
µs
Figure 2.50
Detection of the output stopping
signal from GPT (dead time error,
simultaneous high output, or
simultaneous low output)
tPOEGDO
—
0.1
µs
Figure 2.51
Register setting
tPOEGDS
—
PCLKH +
0.1
µs
Figure 2.52
Oscillation stop detection
tPOEGDOS
—
74
µs
Figure 2.53
Note 1. tPHcyc: PCLKH cycle (LLPP channels), PCLKL cycle (Other channels)
PCLKL, PCLKH
GTETRGn input
(n = A to D)
tPOEGW
Figure 2.49
POEG input timing
Outputs disabled
GPT PWM output pins
POEGGn.PIDF flag
(n = A to D)
GTETRGn input
(n = A to D)
tPOEGW
tPOEGDI
Figure 2.50
Output disable time for POEG via detection flag in response to the input level detection of the
GTETRGn pin
Output stopping signal
from GPT*1
GPT PWM output pins
Outputs disabled
tPOEGDO
Note 1. GPTn.GTST.DTEF (dead time error flag), GPTn.GTST.OABLF (simultaneous low out flag), or GPTn.GTST.OABHF
(simultaneous high output flag)
Figure 2.51
Output disable time for POEG in response to detection of the output stopping signal from GPT
RZ/N2L Datasheet
2. Electrical Characteristics
R01DS0397EJ0120 Rev.1.20
Sep 30, 2022
Page 76 of 127



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