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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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RZ/N2L датащи(PDF) 46 Page - Renesas Technology Corp |
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RZ/N2L датащи(HTML) 46 Page - Renesas Technology Corp |
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46 / 127 page  Table 2.22 Bus timing (2 of 2) Conditions: VOH = VCC33 × 0.5, VOL = VCC33 × 0.5, C = 12 pF (CKIO), 12 pF (others), Tjmin = −20°C Parameter Symbol CKIO = 1/tCKcyc*1 (Max 100 MHz) Unit Reference Figure Min. Max. Read/write delay time 1 SDRAM*2 tRWD1 1.3 8 ns Figure 2.11 to Figure 2.35 Other than the above 0 8 ns Read strobe delay time tRSD 1/2tCKcyc 1/2tCKcyc + 8 ns Figure 2.11 to Figure 2.18 Read data setup time 1*3 High-drive output tRDS1 1/2tCKcyc + 4.5 — ns Figure 2.11 to Figure 2.17 Normal output 1/2tCKcyc + 7 — ns Read data setup time 2*3 High-drive output tRDS2 3.5 — ns Figure 2.19 to Figure 2.22, Figure 2.27 to Figure 2.29 Read data setup time 3*3 High-drive output tRDS3 1/2tCKcyc + 4.5 — ns Figure 2.18 Normal output 1/2tCKcyc + 7 — ns Read data hold time 1 tRDH1 0 — ns Figure 2.11 to Figure 2.17 Read data hold time 2 tRDH2 2.5 — ns Figure 2.19 to Figure 2.22, Figure 2.27 to Figure 2.29 Read data hold time 3 tRDH3 0 — ns Figure 2.18 Write enable delay time 1 tWED1 1/2tCKcyc 1/2tCKcyc + 8 ns Figure 2.11 to Figure 2.16 Write enable delay time 2 tWED2 — 9 ns Figure 2.17 Write data delay time 1 tWDD1 — 8 ns Figure 2.11 to Figure 2.17 Write data delay time 2 tWDD2 — 8 ns Figure 2.23 to Figure 2.26, Figure 2.30 to Figure 2.32 Write data hold time 1 tWDH1 1 — ns Figure 2.11 to Figure 2.17 Write data hold time 2 tWDH2 1.3 — ns Figure 2.23 to Figure 2.26, Figure 2.30 to Figure 2.32 Write data hold time 4 tWDH4 0 — ns Figure 2.11 to Figure 2.15 WAIT# setup time*3 High-drive output tWTS 1/2tCKcyc + 4.5 — ns Figure 2.12 to Figure 2.18 Normal output 1/2tCKcyc + 8 — ns WAIT# hold time tWTH 1/2tCKcyc + 3.5 — ns Figure 2.12 to Figure 2.18 RAS# delay time 1 tRASD1 1.3 8 ns Figure 2.19 to Figure 2.35 CAS# delay time 1 tCASD1 1.3 8 ns Figure 2.19 to Figure 2.35 DQM delay time 1 tDQMD1 1.3 8 ns Figure 2.19 to Figure 2.32 CKE delay time 1 tCKED1 1.3 8 ns Figure 2.34 AH# delay time tAHD 1/2tCKcyc 1/2tCKcyc + 8 ns Figure 2.15 Multiplex address delay time tMAD — 8 ns Figure 2.15 Multiplex address hold time tMAH 1 — ns Figure 2.15 Address setup time to AH# tAVVH 1/2tCKcyc − 2 — ns Figure 2.15 DACK/TEND delay time tDACD See section 2.5.4. DMAC Timing ns Figure 2.11 to Figure 2.32 Note: Notation of 1/2tCKcyc in the delay time, setup time, and hold time shows 1/2 cycles from the clock rising edge, that is, the reference of clock falling. Note 1. Take the number of cycles of waiting that suits the system configuration into consideration with regard to the fmax value for CKIO (the external bus clock). When CKIO is running at 50 MHz or a higher frequency, select high drive output. Note 2. These are values when SDRAM (CSnBCR.TYPE[2:0] = 100b) is selected in the CSn space bus control register (CSnBCR) and high-drive output is selected for CKIO. Note 3. These are values when high-drive output and normal output are respectively selected for CKIO. RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0120 Rev.1.20 Sep 30, 2022 Page 46 of 127 |
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