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RHRPM4423K02V датащи(PDF) 16 Page - STMicroelectronics |
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RHRPM4423K02V датащи(HTML) 16 Page - STMicroelectronics |
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16 / 31 page ![]() 9 Layout and application guidelines The first priority, when components are placed for these applications, is the power section, minimizing the length of each connection and loop. To minimize noise and voltage spikes (EMI and losses as well) power connections have to be a part of a power plane with wide and thick conductor traces: loop has to be minimized. The capacitor on VCC, as well as the output inductor should be placed as closer as possible to IC. Traces between the driver and the external MOSFETs should be short to reduce the inductance of the trace and the ringing in the driving signals. Moreover, the number of vias has to be minimized to reduce the related parasitic effect. Small signal components and connections to critical nodes of the application as well as bypass capacitors for the device supply are also important. The bypass capacitor (VCC capacitors) has to be placed close to the device with the shortest loop to minimize the parasitic inductance. To improve heat dissipation, the copper area has to be placed under the IC. This copper area may be connected to other layers (if available) through vias so to improve the thermal conductivity: the combination of copper pad, copper plane and vias under the driver allows the device to reach its best thermal performance. It is important for the power device to have a thermal path compatible with the dissipated power: both the driver and the external MOSFET have to be mounted on a dedicated heat sink (for example, the driver should be soldered on the copper area of the PCB, which is in strict thermal contact to an aluminum frame) sticking each part to the frame (without using any screw for the MOSFET). The glue could be the resin ME7158 (space approved resin). Moreover, two small FR4 spacers could be added to guarantee the electrical isolation of the package from the frame. A recommended PCB layout is shown in Figure 12. Evaluation board layout: top view. Figure 12. Evaluation board layout: top view GIPD180120161407MT RHRPM4423 Layout and application guidelines DS11827 - Rev 3 page 16/31 |
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